/* sf_loopback_tx.uc
 *
 * This code transmits a flow control packet and then waits for data at the
 * FCIFIFO. When it is received, a check is done on how many packets have
 * been received. If it has not received the expected number of packets,
 * it signals the XScale to extract the payload of the flow control packet
 * received through the FCIFIFO. Then is polls for a signal from the XScale
 * for the DRAM addres for the next packet to transmit. And the code loops
 * around to transmit another low control packet until the expected number
 * of received packets is met. 
 *
 *---------------------------------------------------------------------------
 *                                                                      
 *                  I N T E L   P R O P R I E T A R Y                   
 *                                                                      
 *     COPYRIGHT (c)  2002 BY  INTEL  CORPORATION.  ALL RIGHTS          
 *     RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY      
 *     BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A    
 *     RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER    
 *     LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,    
 *     MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT    
 *     THE PRIOR WRITTEN PERMISSION OF :                                
 *                                                                      
 *                        INTEL  CORPORATION                            
 *                                                                     
 *                     2200 MISSION COLLEGE BLVD                        
 *                                                                      
 *               SANTA  CLARA,  CALIFORNIA  95052-8119                  
 *                                                                      
 *---------------------------------------------------------------------------
 *
 *
 *  system: IXDP2400
 *  subsystem: DIAG
 *  author: dalsraja, March, 2002
 *  revisions:
 * 
 * 
 * --------------------------------------------------------------------------
 */

#include "common_uc.h"

#define TX_ELEMENT_SIZE			MSF_ELEMENTSIZE_128
#define TX_ENABLE_MASK			0x1
#define TX_MODE					MSF_CSIX
#define TX_WIDTH				MSF_WIDTH_1x32
#define TX_SINGLE_PHY			MSF_SINGLE_PHY
#define TBUF_ADDR_SHF			(6 + TX_ELEMENT_SIZE)
#define TX_ELEMENT_SIZE_BYTE	(1 << TBUF_ADDR_SHF)
#define TBUF_ELEM_COUNT			(1 << (7 - TX_ELEMENT_SIZE))				// Tot. elements
#define TBUF_DATA_ELEM_COUNT	((TBUF_ELEM_COUNT >> 2) * 3)		// (Tot. elements / 4) * 3
#define TBUF_CTRL_ELEM_COUNT	(TBUF_ELEM_COUNT - TBUF_DATA_ELEM_COUNT)

#define SCRATCH_ADDRESS			0x400
#define DRAM_BASE_SRC			0x1000000
#define SRAM_BASE_DEST			0x100000

.reg temp offset $pci_rw loops get_ring_num put_ring_num $scratch_data
.reg pkt_count_tx pkt_count_rx refcnt byte_cnt
.reg MsfAddress MsfAddress0 MsfAddress1 tbuf_addr
.reg TxConfigData0
.reg $TxConfigData0
.reg $TxControlWord0 $TxControlWord1
.reg tbuf_element
.reg dram_addr tbuf scratch_addr sram_addr pci_base
.reg payload_len $temp_xfer
.sig dram_sig msf_sig pci_sig sram_sig scratch_sig

.xfer_order $TxControlWord0 $TxControlWord1

br=ctx[0, init#]
ctx_arb[kill]

init#:

#ifdef WORKBENCH_SIM
.begin
	.reg tmp_addr $tmp_data
	.sig scratch_sig

	immed[tmp_addr, 0x200]
wait_for_signal#:
	scratch[read, $tmp_data, tmp_addr, 0, 1], ctx_swap[scratch_sig]
	alu[--, $tmp_data, -, 0]
	bne[wait_for_signal#]
.end
#endif

	immed[tbuf_element, 0]
	immed[pkt_count_tx, 0]

	immed[scratch_addr, SCRATCH_ADDRESS]

	immed[sram_addr, (SRAM_BASE_DEST & MASK_16BIT)]
	immed_w1[sram_addr, ((SRAM_BASE_DEST >> 16) & MASK_16BIT)]
	alu[sram_addr, sram_addr, OR, CHAN_NUMBER, <<SRAM_CHANNEL_NUMBER_FIELD]

	immed[dram_addr, (DRAM_BASE_SRC & MASK_16BIT)]
	immed_w1[dram_addr, ((DRAM_BASE_SRC >> 16) & MASK_16BIT)]

	immed[pci_base, (PCI_LOCAL_CSR_BASE & MASK_16BIT)]
	immed_w1[pci_base, ((PCI_LOCAL_CSR_BASE >> 16) & MASK_16BIT)]

	alu[get_ring_num, --, B, RING_0, <<2]			// ring number in a register
	alu[put_ring_num, --, B, RING_1, <<2]			// ring number in a register


//****************************************************
// Configure TX Control
//****************************************************
	immed[tbuf, RBUF_TBUF]
	immed[MsfAddress, MSF_TX_CONTROL]
	immed[TxConfigData0, (TX_ELEMENT_SIZE << 2)]	// put control and data into diff freelist
	immed_w1[TxConfigData0, ((TX_ENABLE_MASK << 8) | (TX_MODE << 6) | (TX_WIDTH << 4) | (TX_SINGLE_PHY << 3) | (0 << 1) | (1 << 0))]
	alu[$TxConfigData0, --, B, TxConfigData0]
	msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]

	immed_w1[TxConfigData0, ((TX_ENABLE_MASK << 12) | (TX_ENABLE_MASK << 8) | (TX_MODE << 6) | (TX_WIDTH << 4) | (TX_SINGLE_PHY << 3) | (0 << 1) | (1 << 0))]
	alu[$TxConfigData0, --, B, TxConfigData0]
	msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]


//**************************************************
// Configure Scratch Ring
//**************************************************
.begin
	.reg $scratch_base $scratch_head $scratch_tail
	.sig scratch_sig1 scratch_sig2 scratch_sig3

	immed[$scratch_head,0]
	immed[$scratch_tail,0]

	alu[$scratch_base, --, B, 0]	// Use ring size of 128 lw and base 0x0
	cap[write, $scratch_base, SCRATCH_RING_BASE_0], sig_done[scratch_sig1]
	cap[write, $scratch_head, SCRATCH_RING_HEAD_0], sig_done[scratch_sig2]
	cap[write, $scratch_tail, SCRATCH_RING_TAIL_0], sig_done[scratch_sig3]
	ctx_arb[scratch_sig1, scratch_sig2, scratch_sig3]

	alu[$scratch_base, --, B, 1, <<9]	// Use ring size of 128 lw and base 0x200
	cap[write, $scratch_base, SCRATCH_RING_BASE_1], sig_done[scratch_sig1]
	cap[write, $scratch_head, SCRATCH_RING_HEAD_1], sig_done[scratch_sig2]
	cap[write, $scratch_tail, SCRATCH_RING_TAIL_1], sig_done[scratch_sig3]
	ctx_arb[scratch_sig1, scratch_sig2, scratch_sig3]
.end

immed[pkt_count_rx, 0]

next_packet#:
#ifndef WORKBENCH_SIM
wait_for_data#:
	scratch[get, $scratch_data, get_ring_num, 0, 1], ctx_swap[scratch_sig]
	alu[--, $scratch_data, -, 0]
	beq[wait_for_data#]			// If 0, check again

	alu[byte_cnt, --, B, $scratch_data]
#else
	immed[byte_cnt, 64]
#endif


//****************************************************
// Move data to TBUF from DRAM
//****************************************************
transmit#:
	alu[tbuf_addr, tbuf, OR, tbuf_element, <<TBUF_ADDR_SHF]

	alu[tbuf_addr, --, B, tbuf_addr, <<5]
	alu[tbuf_addr, tbuf_addr, OR, 1, <<4]		// set the overwrite bit for the TBUF addr
	alu[refcnt, --, B, byte_cnt, >>3]
	alu[--, byte_cnt, AND, 0x7]
	beq[cont1#]
	alu[refcnt, refcnt, +, 1]			// Calculate the refcnt for indirect ref
cont1#:
	alu[refcnt, --, B, refcnt, <<21]	// Shift to appropriate bit
	alu[refcnt, refcnt, OR, 1, <<25]	// Set the overwrite bit for refcnt
	alu[--, tbuf_addr, OR, refcnt]	// indirect ref
	dram[tbuf_wr, --, dram_addr, 0, 8], indirect_ref, sig_done[dram_sig]
	ctx_arb[dram_sig]

#ifdef MSF_WORKAROUND
	alu[--, --, B, tbuf_addr]	// indirect ref
	dram[tbuf_wr, --, dram_addr, 0, 2], indirect_ref, sig_done[dram_sig]
	ctx_arb[dram_sig]
#endif


//*******************************************************
// Write the Transmit Control Word with appropriate data
//*******************************************************
	immed[$TxControlWord1, 0]		// No extension header for flow control packet
	immed[temp, CSIX_FLOWCONTROL]
	alu[$TxControlWord0, temp, OR, byte_cnt, <<24]
	immed[MsfAddress, TBUF_ELEMENT_CONTROL_V]
	alu[MsfAddress, MsfAddress, OR, tbuf_element, <<3] //TBUF_CTRL_ADDR_SHF
	msf[write, $TxControlWord0, MsfAddress, 0, 2], ctx_swap[msf_sig]		// Write control word and validate

	alu[pkt_count_tx, pkt_count_tx, +, 1]
	alu[tbuf_element, tbuf_element, +, 1]
	
	.if (tbuf_element == TBUF_DATA_ELEM_COUNT)
		immed[tbuf_element, 0]
	.endif
	
// Wait for FCIFIFO data (through CBUS)
	immed[byte_cnt, 0]
	immed[MsfAddress, FCIFIFO]

wait_for_fcififo#:
	br_!inp_state[fci_not_empty, wait_for_fcififo#]		// Branch to label is FCIFIFO empty
	msf[read, $temp_xfer, MsfAddress, 0, 1], ctx_swap[msf_sig]	// Read FCIFIFO
	alu[payload_len, 0xFF, AND, $temp_xfer, >>16]				// extract payload length

process_fcififo_data#:
	alu[$temp_xfer, --, B, $temp_xfer]
	scratch[write, $temp_xfer, scratch_addr, byte_cnt, 1], ctx_swap[scratch_sig]
	alu[byte_cnt, byte_cnt, +, 4]	// Inc byte count by 4 as a long word was read from FCIFIFO

read_fcififo#:
	br_!inp_state[fci_not_empty, fcififo_empty#]	// Branch to label if FCIFIFO empty
	msf[read, $temp_xfer, MsfAddress, 0, 1], ctx_swap[msf_sig]		// Read FCIFIFO
	br[process_fcififo_data#]

fcififo_empty#:				// FCIFIFO is now empty
#ifndef WORKBENCH_SIM
	alu[$scratch_data, --, B, byte_cnt]
	scratch[put, $scratch_data, put_ring_num, 0, 1], ctx_swap[scratch_sig]
#endif
	
	alu[pkt_count_rx, pkt_count_rx, +, 1]	// Increment the received packet count

	br[next_packet#]