?? sys_loopback_bw_eg_tx.uc
字號:
/* sys_loopback_eg_tx.uc
*
* This file transmits POS packets from DRAM. If the number of transmitted
* packets is not equals to the number that have to be transmitted, it polls
* on scratch for a signal from the receive ME. When it receives the signal
* from the receive ME, it extracts the DRAM address where the packet to be
* transmitted is stored and transmits it. If the number of transmitted
* packets is equal to the number that have to be transmitted, it signals the
* XScale that it has completed all the transmitting.
*
*---------------------------------------------------------------------------
*
* I N T E L P R O P R I E T A R Y
*
* COPYRIGHT (c) 2002 BY INTEL CORPORATION. ALL RIGHTS
* RESERVED. NO PART OF THIS PROGRAM OR PUBLICATION MAY
* BE REPRODUCED, TRANSMITTED, TRANSCRIBED, STORED IN A
* RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER
* LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,
* MAGNETIC, OPTICAL, CHEMICAL, MANUAL, OR OTHERWISE, WITHOUT
* THE PRIOR WRITTEN PERMISSION OF :
*
* INTEL CORPORATION
*
* 2200 MISSION COLLEGE BLVD
*
* SANTA CLARA, CALIFORNIA 95052-8119
*
*---------------------------------------------------------------------------
*
*
* system: IXDP2400
* subsystem: DIAG
* author: dalsraja, April, 2002
* revisions: dalsraja, May 8, 2002
*
*
* --------------------------------------------------------------------------
*/
#include "common_uc.h"
#define TX_ELEMENT_SIZE MSF_ELEMENTSIZE_128
#define TX_ENABLE_MASK 0xF
#define TX_MODE MSF_POS_UTOPIA
#define TX_WIDTH MSF_WIDTH_4x8
#define TX_SINGLE_PHY MSF_SINGLE_PHY
#define TX_CONTROL_EOP (1 << 8)
#define TX_CONTROL_SOP (1 << 9)
#define SOPEOP_SHF 8
#define TBUF_ELEM_COUNT (1 << (7 - TX_ELEMENT_SIZE))
#define TBUF_ELEM_COUNT_4PORT (TBUF_ELEM_COUNT >> 2)
#define TBUF_ELEM_MASK_4PORT ((TBUF_ELEM_COUNT >> 2) - 1)
#define TBUF_ADDR_SHF (6 + TX_ELEMENT_SIZE)
#define TX_ELEMENTSIZE_BYTE (1 << TBUF_ADDR_SHF)
#define ME_NUMBER_RX 0
#define ME_NUMBER_TX 1
#define RX_THD_NUM 0
#define INTERTHD_SIG_NUM 15
#define SCRATCH_MESSAGE_BASE 0x1000
#ifdef WORKBENCH_SIM
#define ORIG_PKT_DRAM_ADDR 0x1000000 // Original packet stored in 16 Meg
#define ORIG_PACKET_SIZE 64
#define MESSAGE_ADDR 0x1200
#endif
.reg scratch_addr get_ring_num put_ring_num
.reg total_byte_count byte_count tx_count @total_pkt_count
.reg cur_me cur_ctx
.reg packet_status packet_size sopeop
.reg $TxControlWord0 $TxControlWord1
.reg tbuf tbuf_element tbuf_mask tbuf_1st_element
.reg dram_base dram_addr
.reg $scratch_data0 $scratch_data1
.sig dram_sig msf_sig interthd_sig cap_sig scratch_sig
.addr interthd_sig INTERTHD_SIG_NUM
.xfer_order $TxControlWord0 $TxControlWord1
.xfer_order $scratch_data0 $scratch_data1
.set_sig interthd_sig
br=ctx[0, init#]
br=ctx[1, init#]
br=ctx[2, init#]
br=ctx[3, init#]
ctx_arb[kill]
init#:
.local temp
local_csr_rd[ACTIVE_CTX_STS]
immed[temp, 0]
alu[cur_me, MASK_4BIT, AND, temp, >>SHIFT_3] // Extract the current ME number
alu[cur_ctx, MASK_3BIT, AND, temp] // Extract the current context number
.endlocal
immed[tbuf, RBUF_TBUF]
immed[tbuf_mask, TBUF_ELEM_MASK_4PORT]
alu[tbuf_1st_element, --, B, cur_ctx, <<(TBUF_ELEM_COUNT_4PORT >> SHIFT_2)]
immed[tx_count, 0]
immed[@total_pkt_count, 0]
#ifdef WORKBENCH_SIM
immed[dram_base, (ORIG_PKT_DRAM_ADDR & MASK_16BIT)]
immed_w1[dram_base, ((ORIG_PKT_DRAM_ADDR >> SHIFT_16) & MASK_16BIT)]
#else
immed[scratch_addr, SCRATCH_MESSAGE_BASE]
scratch[read, $scratch_data0, scratch_addr, 0, 1], ctx_swap[scratch_sig]
alu[dram_base, --, B, $scratch_data0]
#endif
immed[packet_status, 0]
alu[get_ring_num, --, B, cur_ctx, <<2]
alu[put_ring_num, --, B, RING_4, <<2]
.set_sig interthd_sig
ctx_arb[interthd_sig]
br!=ctx[0, get_packet_data#]
.local MsfAddress TxConfigData0 $TxConfigData0
//****************************************************
// Configure TX Control
//****************************************************
immed[MsfAddress, MSF_TX_CONTROL]
immed[TxConfigData0, (TX_ELEMENT_SIZE << 2)] // put control and data into diff freelist
immed_w1[TxConfigData0, ((TX_ENABLE_MASK << 8) | (TX_MODE << 6) | (TX_WIDTH << 4) | (TX_SINGLE_PHY << 3) | (0<<1)|(1<<0))]
alu[$TxConfigData0, --, B, TxConfigData0]
msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
//******************************************************
// Configure TX UP Control CSRs
//******************************************************
immed[TxConfigData0, (UP_CTRL_CP_MODE | UP_CTRL_PARITY | UP_CTRL_CELLSIZE | UP_CTRL_DRTIME)]
immed[MsfAddress, TX_UP_CONTROL_0]
alu[$TxConfigData0, --, B, TxConfigData0]
msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, TX_UP_CONTROL_1]
alu[$TxConfigData0, --, B, TxConfigData0]
msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, TX_UP_CONTROL_2]
alu[$TxConfigData0, --, B, TxConfigData0]
msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, TX_UP_CONTROL_3]
alu[$TxConfigData0, --, B, TxConfigData0]
msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
//****************************************************
// Configure TX Control
//****************************************************
immed[MsfAddress, MSF_TX_CONTROL]
immed[TxConfigData0, (TX_ELEMENT_SIZE << 2)] // put control and data into diff freelist
immed_w1[TxConfigData0, ((TX_ENABLE_MASK << 12) | (TX_ENABLE_MASK << 8) | (TX_MODE << 6) | (TX_WIDTH << 4) | (TX_SINGLE_PHY << 3) | (0<<1)|(1<<0))]
alu[$TxConfigData0, --, B, TxConfigData0]
msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
.endlocal
local_csr_wr[SAME_ME_SIGNAL, ((INTERTHD_SIG_NUM << 3) | 1)]
local_csr_wr[SAME_ME_SIGNAL, ((INTERTHD_SIG_NUM << 3) | 2)]
local_csr_wr[SAME_ME_SIGNAL, ((INTERTHD_SIG_NUM << 3) | 3)]
get_packet_data#:
#ifdef WORKBENCH_SIM
.if (cur_ctx == 0)
immed[packet_size, 48]
immed[dram_addr, 0]
alu[dram_addr, dram_base, +, dram_addr]
.elif (cur_ctx == 1)
immed[packet_size, 64]
immed[dram_addr, 0x200]
alu[dram_addr, dram_base, +, dram_addr]
.elif (cur_ctx == 2)
immed[packet_size, 136]
immed[dram_addr, 0x400]
alu[dram_addr, dram_base, +, dram_addr]
.else
immed[packet_size, 64]
immed[dram_addr, 0x600]
alu[dram_addr, dram_base, +, dram_addr]
.endif
#else
scratch[get, $scratch_data0, get_ring_num, 0, 1], ctx_swap[scratch_sig]
alu[--, $scratch_data0, -, 0]
beq[get_packet_data#] // branch to label if there is no new assignment
alu[packet_size, 0, +16, $scratch_data0]
alu[dram_addr, --, B, $scratch_data0, >>16]
alu[dram_addr, --, B, dram_addr, <<8]
alu[dram_addr, dram_base, +, dram_addr]
#endif
/*
.begin
.reg scratch_add $s_xfer tmp_val
immed[scratch_add, 0x1200]
alu[scratch_add, scratch_add, OR, cur_ctx, <<2]
alu[tmp_val, --, B, dram_addr]
alu[$s_xfer, --, B, tmp_val]
scratch[write, $s_xfer, scratch_add, 0, 1], ctx_swap[scratch_sig]
.end
*/
transmit#:
//****************************************************
// Move data to TBUF from DRAM
//****************************************************
.begin
.reg cur_tbuf_addr refcnt
alu[tbuf_element, tbuf_1st_element, +, tx_count]
.if (packet_status == 0)
.if (packet_size <= TX_ELEMENTSIZE_BYTE)
alu[byte_count, --, B, packet_size]
immed[sopeop, SOP_EOP]
.else
immed[byte_count, TX_ELEMENTSIZE_BYTE]
immed[sopeop, SOP_NOEOP]
.endif
.else
alu[byte_count, packet_size, -, packet_status]
.if (byte_count > TX_ELEMENTSIZE_BYTE)
immed[byte_count, TX_ELEMENTSIZE_BYTE]
immed[sopeop, MOP]
.else
immed[sopeop, NOSOP_EOP]
.endif
.endif
alu[cur_tbuf_addr, tbuf, OR, tbuf_element, <<TBUF_ADDR_SHF]
alu[cur_tbuf_addr, --, B, cur_tbuf_addr, <<5]
alu[cur_tbuf_addr, cur_tbuf_addr, OR, 1, <<4] // set the overwrite bit for the TBUF addr
alu[refcnt, --, B, byte_count, >>3]
alu[--, byte_count, AND, 0x7]
beq[cont1#]
alu[refcnt, refcnt, +, 1] // Calculate the refcnt for indirect ref
cont1#:
.if (refcnt > 15) // This is assuming that the RBUF Element are always 128 bytes
immed[refcnt, 15]
.endif
alu[refcnt, --, B, refcnt, <<21] // Shift to appropriate bit
alu[refcnt, refcnt, OR, 1, <<25] // Set the overwrite bit for refcnt
alu[--, cur_tbuf_addr, OR, refcnt] // indirect ref
dram[tbuf_wr, --, dram_addr, packet_status, 8], indirect_ref, sig_done[dram_sig]
ctx_arb[dram_sig]
.end
//*******************************************************
// Write the Transmit Control Word with appropriate data
//*******************************************************
.begin
.reg temp MsfAddress
immed[MsfAddress, TBUF_ELEMENT_CONTROL_V]
alu[MsfAddress, MsfAddress, OR, tbuf_element, <<3] //TBUF_CTRL_ADDR_SHF
alu[temp, --, B, sopeop, <<SOPEOP_SHF]
alu[$TxControlWord0, temp, OR, byte_count, <<24]
immed[$TxControlWord1, 0]
msf[write, $TxControlWord0, MsfAddress, 0, 2], ctx_swap[msf_sig]
.end
alu[tx_count, tx_count, +, 1]
alu[tx_count, tbuf_mask, AND, tx_count]
alu[packet_status, packet_status, +, byte_count]
.if (packet_size != packet_status)
br[transmit#]
.endif
immed[packet_status, 0]
alu[@total_pkt_count, @total_pkt_count, +, 1]
#ifndef WORKBENCH_SIM
ring_full#:
br_inp_state[SCR_Ring4_Full, ring_full#]
alu[$scratch_data0, --, B, @total_pkt_count]
scratch[put, $scratch_data0, put_ring_num, 0, 1], ctx_swap[scratch_sig]
#endif
br[get_packet_data#]
/*
.begin
.reg scratch_add $s_xfer tmp_val
// alu[tmp_val, dram_addr, +, packet_status]
alu[$s_xfer, --, B, $scratch_data0]
scratch[write, $s_xfer, scratch_add, 0, 1], ctx_swap[scratch_sig]
alu[scratch_add, scratch_add, +, 4]
.end
*/
/*
.begin
.reg scratch_add $s_xfer
immed[scratch_add, 0x40C]
alu[$s_xfer, --, B, packet_count]
scratch[write, $s_xfer, scratch_add, 0, 1], ctx_swap[scratch_sig]
.end
*/
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