?? sys_loopback_bd_2_in_tx.uc
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/* sys_loopback_bd_2_in_tx.uc
*
*---------------------------------------------------------------------------
*
* I N T E L P R O P R I E T A R Y
*
* COPYRIGHT (c) 2002 BY INTEL CORPORATION. ALL RIGHTS
* RESERVED. NO PART OF THIS PROGRAM OR PUBLICATION MAY
* BE REPRODUCED, TRANSMITTED, TRANSCRIBED, STORED IN A
* RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER
* LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,
* MAGNETIC, OPTICAL, CHEMICAL, MANUAL, OR OTHERWISE, WITHOUT
* THE PRIOR WRITTEN PERMISSION OF :
*
* INTEL CORPORATION
*
* 2200 MISSION COLLEGE BLVD
*
* SANTA CLARA, CALIFORNIA 95052-8119
*
*---------------------------------------------------------------------------
*
*
* system: IXDP2400
* subsystem: DIAG
* author: dalsraja, April, 2002
* revisions: dalsraja, May 8, 2002
*
*
* --------------------------------------------------------------------------
*/
#include "common_uc.h"
#include "sys_loopback_bd_2.h"
#define TX_ENABLE_MASK 0x1
#define TX_MODE MSF_CSIX
#define TX_WIDTH MSF_WIDTH_1x32
#define TX_SINGLE_PHY MSF_SINGLE_PHY
#define TX_ELEMENTSIZE MSF_ELEMENTSIZE_128
#define TBUF_ELEM_COUNT (((1 << (7 - TX_ELEMENTSIZE)) >> 2) * 3) // Tot. elements
#define TBUF_ADDR_SHF (6 + TX_ELEMENTSIZE)
#define Tx_ELEMENTSIZE_BYTE (1 << TBUF_ADDR_SHF)
#define TBUF_CTRL_ADDR_SHF (3 + TX_ELEMENTSIZE)
#define CSIX_TYPE_UNICAST 1 // CSIX Type = Unicast
#define EXT_HDR 0
#define SRAM_DESC_BASE 0x200000 // 4 Meg onwards
#define DRAM_PCKT_BASE 0x1000000 // 16 Meg onwards
#define ME_NUMBER_RX 0
#define ME_NUMBER_TX 1
#define RX_THD_NUM 0
#define TX_THD_NUM 0
#define INTER_ME_SIG_NUM 15
#define NEXT_CTX_SIGNAL &next_ctx_sig
#define SIG_CTX (0x80 | NEXT_CTX_SIGNAL << 3)
#define BUFFER_ADDR_MASK 0xFFFFFF
.reg sram_addr
.reg temp $temp
.reg MsfAddress MsfAddress0 MsfAddress1
.reg byte_count ring_num mask_qa
.reg TxConfigData0
.reg $TxConfigData0
.reg $TxControlWord0 $TxControlWord1
.reg $scratch_data0 $scratch_data1
.reg @tbuf_element cur_tbuf_elem
.reg buf_addr pkt_buff_addr tbuf tbuf_mask cur_tbuf_addr
.reg @sramDescBase @dramPacketBase @t0
.sig dram_sig msf_sig interthd_sig cap_sig scratch_sig next_ctx_sig
.sig sram_sig
.reg @total_tx
.xfer_order $TxControlWord0 $TxControlWord1
.xfer_order $scratch_data0 $scratch_data1
.addr interthd_sig INTER_ME_SIG_NUM
.set_sig interthd_sig next_ctx_sig
init_common#:
immed[mask_qa, (BUFFER_ADDR_MASK & MASK_16BIT)]
immed_w1[mask_qa, ((BUFFER_ADDR_MASK >> 16) & MASK_16BIT)] // Used to mask out the buffer address on dequeue
immed[ring_num, RING_0]
immed[tbuf, RBUF_TBUF]
immed[tbuf_mask, TBUF_Elem_Count]
alu[tbuf_mask, tbuf_mask, -, 1]
br!=ctx[0, wait_for_next_ctx_sig#]
init#:
immed[@tbuf_element, 0]
immed[@total_tx, 0]
immed[@sramDescBase, (SRAM_DESC_BASE & MASK_16BIT)]
immed_w1[@sramDescBase, ((SRAM_DESC_BASE >> 16) & MASK_16BIT)]
immed[@dramPacketBase, (DRAM_PCKT_BASE & MASK_16BIT)]
immed_w1[@dramPacketBase, ((DRAM_PCKT_BASE >> 16) & MASK_16BIT)]
.begin
.reg channel_number
alu[channel_number, --, B, CHAN_NUMBER, <<SRAM_CHANNEL_NUMBER_FIELD]
alu[channel_number, channel_number, OR, Q_NUMBER, <<SRAM_Q_ARRAY_NUMBER_FIELD]
alu[@t0, --, B, channel_number]
.end
//****************************************************
// Configure TX Control
//****************************************************
immed[MsfAddress, MSF_TX_CONTROL]
immed[TxConfigData0, (TX_ELEMENTSIZE << 2)] // put control and data into diff freelist
immed_w1[TxConfigData0, ((TX_ENABLE_MASK << 8) | (TX_MODE << 6) | (TX_WIDTH << 4) | (TX_SINGLE_PHY << 3) | (0<<1)|(1<<0))]
alu[$TxConfigData0, --, B, TxConfigData0]
msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
immed[MsfAddress, MSF_TX_CONTROL]
immed[TxConfigData0, (TX_ELEMENTSIZE << 2)] // put control and data into diff freelist
immed_w1[TxConfigData0, ((TX_ENABLE_MASK << 12) | (TX_ENABLE_MASK << 8) | (TX_MODE << 6) | (TX_WIDTH << 4) | (TX_SINGLE_PHY << 3) | (0<<1)|(1<<0))]
alu[$TxConfigData0, --, B, TxConfigData0]
msf[write, $TxConfigData0, MsfAddress, 0, 1], ctx_swap[msf_sig]
//**************************************************
// Configure Scratch Ring
//**************************************************
.begin
.reg $scratch_base $scratch_head $scratch_tail
.sig scratch_sig1 scratch_sig2 scratch_sig3
// immed[$scratch_base,0x200]
alu[$scratch_base, --, B, 0xC, <<28] // Use ring size of 1024 lw and base 0x0
immed[$scratch_head,0]
immed[$scratch_tail,0]
cap[write,$scratch_base,SCRATCH_RING_BASE_0],sig_done[scratch_sig1]
cap[write,$scratch_head,SCRATCH_RING_HEAD_0],sig_done[scratch_sig2]
cap[write,$scratch_tail,SCRATCH_RING_TAIL_0],sig_done[scratch_sig3]
ctx_arb[scratch_sig1, scratch_sig2, scratch_sig3]
.end
immed[temp, ((ME_NUMBER_RX << 7) | (RX_THD_NUM << 4) | (INTER_ME_SIG_NUM << 0))]
alu[--, --, B, temp]
cap[fast_wr, ALU, interthread_sig] // to signal Rx ME that Tx has finished its init
br[wait_for_assignment#]
wait_for_next_ctx_sig#:
.set_sig next_ctx_sig
ctx_arb[next_ctx_sig]
wait_for_assignment#:
// scratch[get, $scratch_data0, ring_num, 0, 1], ctx_swap[scratch_sig]
scratch[get, $scratch_data0, ring_num, 0, 1], sig_done[scratch_sig]
waiting_for_signal#:
br_!signal[scratch_sig, waiting_for_signal#]
alu[--, $scratch_data0, -, 0]
beq[wait_for_assignment#] // branch to label if there is no new assignment
local_csr_wr[SAME_ME_SIGNAL, SIG_CTX]
alu[buf_addr, mask_qa, AND, $scratch_data0]
alu[byte_count, --, B, $scratch_data0, >>24]
alu[cur_tbuf_elem, --, B, @tbuf_element]
alu[@tbuf_element, @tbuf_element, +, 1]
alu[--, TBUF_ELEM_COUNT, -, @tbuf_element]
bne[transmit#]
alu[@tbuf_element, --, B, 0]
transmit#:
//****************************************************
// Move data to TBUF from DRAM
//****************************************************
.begin
.reg refcnt pkt_buf_addr
.set_sig next_ctx_sig
alu[pkt_buf_addr, --, B, buf_addr, <<5]
alu[pkt_buf_addr, pkt_buf_addr, +, @dramPacketBase]
alu[cur_tbuf_addr, tbuf, OR, cur_tbuf_elem, <<TBUF_ADDR_SHF]
alu[cur_tbuf_addr, --, B, cur_tbuf_addr, <<5]
alu[cur_tbuf_addr, cur_tbuf_addr, OR, 1, <<4] // set the overwrite bit for the TBUF addr
alu[refcnt, --, B, byte_count, >>3]
alu[--, byte_count, AND, 0x7]
bne[cont1#]
alu[refcnt, refcnt, -, 1] // Calculate the refcnt for indirect ref
cont1#:
// local_csr_wr[SAME_ME_SIGNAL, SIG_CTX]
alu[refcnt, --, B, refcnt, <<21] // Shift to appropriate bit
alu[refcnt, refcnt, OR, 1, <<25] // Set the overwrite bit for refcnt
alu[--, cur_tbuf_addr, OR, refcnt] // indirect ref
dram[tbuf_wr, --, pkt_buf_addr, 0, 8], indirect_ref, sig_done[dram_sig]
ctx_arb[dram_sig/*, next_ctx_sig*/]
.end
//*******************************************************
// Write the Transmit Control Word with appropriate data
//*******************************************************
.begin
.reg MsfAddress
.set_sig next_ctx_sig
// local_csr_wr[SAME_ME_SIGNAL, SIG_CTX]
immed[MsfAddress, TBUF_ELEMENT_CONTROL_V]
alu[MsfAddress, MsfAddress, OR, cur_tbuf_elem, <<3] //TBUF_CTRL_ADDR_SHF
immed[temp, CSIX_TYPE_UNICAST]
alu[$TxControlWord0, temp, OR, byte_count, <<24] // For Tx Control Word
immed[temp, (EXT_HDR & MASK_16BIT)]
immed_w1[temp, ((EXT_HDR >> 16) & MASK_16BIT)]
alu[$TxControlWord1, --, B, temp] // Setting extension header
msf[write, $TxControlWord0, MsfAddress, 0, 2], sig_done[msf_sig]
ctx_arb[msf_sig, next_ctx_sig]
/*
alu[@total_tx, @total_tx, +, 1]
.begin
.reg temp_scratch_addr $pkt_number
alu[$pkt_number, --, B, @total_tx]
immed[temp_scratch_addr, (SCRATCH_MSG_ADDR + PKTS_TX_OFFSET)]
scratch[write, $pkt_number, temp_scratch_addr, 0, 1], ctx_swap[scratch_sig]
.end
*/
.end
//*******************************************************
// Free buffer
//*******************************************************
.begin
.reg temp cellcount t0
local_csr_wr[SAME_ME_SIGNAL, SIG_CTX]
alu[t0, --, B, @t0]
alu[temp, @sramDescBase, +, buf_addr]
alu[temp, --, B, temp, >>2]
immed[cellcount, 0x1c, <<16] // set OV EOP, and SOP
alu[--, cellcount, OR, 0]
sram[enqueue, --, t0, temp], indirect_ref
.end
br[wait_for_assignment#]
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