/* Register_Test.uc
 *
 *---------------------------------------------------------------------------
 *                                                                      
 *                  I N T E L   P R O P R I E T A R Y                   
 *                                                                      
 *     COPYRIGHT (c)  2002 BY  INTEL  CORPORATION.  ALL RIGHTS          
 *     RESERVED.   NO  PART  OF THIS PROGRAM  OR  PUBLICATION  MAY      
 *     BE  REPRODUCED,   TRANSMITTED,   TRANSCRIBED,   STORED  IN  A    
 *     RETRIEVAL SYSTEM, OR TRANSLATED INTO ANY LANGUAGE OR COMPUTER    
 *     LANGUAGE IN ANY FORM OR BY ANY MEANS, ELECTRONIC, MECHANICAL,    
 *     MAGNETIC,  OPTICAL,  CHEMICAL, MANUAL, OR OTHERWISE,  WITHOUT    
 *     THE PRIOR WRITTEN PERMISSION OF :                                
 *                                                                      
 *                        INTEL  CORPORATION                            
 *                                                                     
 *                     2200 MISSION COLLEGE BLVD                        
 *                                                                      
 *               SANTA  CLARA,  CALIFORNIA  95052-8119                  
 *                                                                      
 *---------------------------------------------------------------------------
 *
 *
 *  system: IXP2000
 *  subsystem: DIAG
 *  author: ccm, Mar 15, 02
 * 
 * --------------------------------------------------------------------------
 */

#include "../../../include/me_xscale_sync.h"

.sig dram_write dram_read
.sig sram_write sram_read
.sig scratch_write scratch_read

.reg A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15
.reg B0, B1, B2, B3, B4, B5, B6, B7, B8, B9, B10, B11, B12, B13, B14, B15

.reg $SW0 $SW1 $SW2 $SW3 $SW4 $SW5 $SW6 $SW7 $SW8 $SW9 $SW10 $SW11 $SW12 $SW13 $SW14 $SW15
.reg $SR0 $SR1 $SR2 $SR3 $SR4 $SR5 $SR6 $SR7 $SR8 $SR9 $SR10 $SR11 $SR12 $SR13 $SR14 $SR15
.xfer_order $SW0 $SW1 $SW2 $SW3 $SW4 $SW5 $SW6 $SW7 $SW8 $SW9 $SW10 $SW11 $SW12 $SW13 $SW14 $SW15
.xfer_order $SR0 $SR1 $SR2 $SR3 $SR4 $SR5 $SR6 $SR7 $SR8 $SR9 $SR10 $SR11 $SR12 $SR13 $SR14 $SR15

.reg $$DW0 $$DW1 $$DW2 $$DW3 $$DW4 $$DW5 $$DW6 $$DW7 $$DW8 $$DW9 $$DW10 $$DW11 $$DW12 $$DW13 $$DW14 $$DW15
.reg $$DR0 $$DR1 $$DR2 $$DR3 $$DR4 $$DR5 $$DR6 $$DR7 $$DR8 $$DR9 $$DR10 $$DR11 $$DR12 $$DR13 $$DR14 $$DR15
.xfer_order $$DW0 $$DW1 $$DW2 $$DW3 $$DW4 $$DW5 $$DW6 $$DW7 $$DW8 $$DW9 $$DW10 $$DW11 $$DW12 $$DW13 $$DW14 $$DW15
.xfer_order $$DR0 $$DR1 $$DR2 $$DR3 $$DR4 $$DR5 $$DR6 $$DR7 $$DR8 $$DR9 $$DR10 $$DR11 $$DR12 $$DR13 $$DR14 $$DR15

#define NUM_OF_NN_TO_TEST 128	// max 128
#define LM_TO_TEST 	640	// max 640

#define XFER_REG_TEST			// Stores status at scratch location 0 - 127
#define GPR_TESTS				// Stores status at scratch location 128 - 255
#define LOCAL_MEM_TEST			// Stores status at scratch location 256 - 287
#define NEXT_NEIGHBOR_TEST	// Stores status at scratch location 288 - 319

#define LMA_TEST_VAL 100000
#define X 0

#define ME 0

// Manual allocation of all GPR-A AND GPR-B
#WHILE(X < 16)
	.areg A/**/X X
	.breg B/**/X X
	#define_eval X (X + 1)
#ENDLOOP

/************************/
/*	TRANSFER REG TEST	*/
/************************/
// Requires 317 uword instructions
// ***** NOTE *****: Assumes GPR A0, A1 and B0 works
// A0 is used for storing the ctx number
TRANSFER_REG_TEST#:
#ifdef XFER_REG_TEST

// Obtain ctx number
local_csr_rd[active_ctx_sts]
immed[A0, 0]
alu[A0, 0x7, AND, A0]

// ***** Init SRAM and DRAM xfer regs *****
// Init values for SW[x]: SW[x] = x + 1 + ME<<4
// Init values for DW[x]: DW[x] = x + 1 + ME<<4 + 100
#define_eval X 0
#WHILE(X < 16)
	immed[B0, (X + 1)]
	alu[B0, B0, OR, A0, <<6]
	alu[$SW/**/X,  --, B, B0]
	immed[B0, (X + 1 + 512)]
	alu[B0, B0, OR, A0, <<6]
	alu[$$DW/**/X,  --, B, B0]
	#define_eval X (X + 1)
#ENDLOOP

// ***** Calculate addr for each thd to write and read back from memory *****
// to obtain ctx offset
// ctx number multiply 16, (<<4) to obtain offset
alu[A1, --, B, A0, <<4]

//********************************************************************
// calculate ME (make it between 0-7) and put it into B1
local_csr_rd[active_ctx_sts]
immed[B1, 0]
alu_shf[B1, 0x1f, AND, B1, >>3]
alu[--, B1, -, 0x3]
ble[me0_me3_0#]

alu[B1, 0x3, AND, B1]
alu[B1, 0x4, OR, B1]
br[me_obtain0#]

me0_me3_0#:
alu[B1, 0x3, AND, B1]

me_obtain0#:
//********************************************************************

// ME number offset
alu_shf[A1, A1, OR, B1, <<7]
alu_shf[A1, A1, OR, 1, <<10]

// ***** Write and Read back SRAM and DRAM memory *****
alu[A2, --, B, A1, <<2]	// shifted to access in Lword
alu [--, --, B, 0x1f, <<21]		//set ref count to be over-written with 16
scratch[write, $SW0, A2, 0, 8], indirect_ref, ctx_swap[sram_write]
alu [--, --, B, 0x1f, <<21]		//set ref count to be over-written with 16
scratch[read, $SR0, A2, 0, 8], indirect_ref, ctx_swap[sram_read]

immed[B1, 0x4, <<16]	// set DRAM_BASE = 2MB
alu[A1, A1, OR, B1]
alu[A1, --, B, A1, <<3]	// shifted to access in Qword (from Lword)
dram[write, $$DW0, A1, 0, 8], sig_done[dram_write]
ctx_arb[dram_write]
dram[read, $$DR0, A1, 0, 8], sig_done[dram_read]
ctx_arb[dram_read]

// ***** Check S_XFER_REG and D_XFER_REG *****
// Errors in SRAM xfer0-xfer15 will reside in lower 16 bits of A0
// Errors in DRAM xfer0-xfer15 will reside in higher 16 bits of A0

immed[A1, 0]	// Errors will be ORed into the respective bit of A0
#define_eval X 0
#WHILE(X < 16)
	// Check S xfer
	immed[B0, (X + 1)]
	alu[B0, B0, OR, A0, <<6]
	alu[--, $SR/**/X, -,  B0]
	bne[SRAM_XFER_REG_ERROR/**/X/**/#]
	SRAM_XFER_REG_CONT/**/X/**/#:

	// Check D xfer
	immed[B0, (X + 1 + 512)]
	alu[B0, B0, OR, A0, <<6]
	alu[--, $$DR/**/X, -, B0]
	bne[DRAM_XFER_REG_ERROR/**/X/**/#]
	DRAM_XFER_REG_CONT/**/X/**/#:

	#define_eval X (X + 1)
#ENDLOOP

br[XFER_REG_TEST_WRITE_STATUS#]


// ***** S XFER REG ERROR REPORTING *****
#define Y 16
#define_eval X 0
#WHILE(X < 16)
	SRAM_XFER_REG_ERROR/**/X/**/#:
	alu_shf[A1, A1, OR, 1, <<Y]
	br[SRAM_XFER_REG_CONT/**/X/**/#]
	#define_eval X (X + 1)
	#define_eval Y (Y + 1)
#ENDLOOP
#undef Y

// ***** D XFER REG ERROR REPORTING ******
#define Y 0
#define_eval X 0
#WHILE(X < 16)
	DRAM_XFER_REG_ERROR/**/X/**/#:
	alu_shf[A1, A1, OR, 1, <<Y]
	br[DRAM_XFER_REG_CONT/**/X/**/#]
	#define_eval X (X + 1)
	#define_eval Y (Y + 1)
#ENDLOOP
#undef Y

// ***** WRITE STATUS TO SCRATCH *****
XFER_REG_TEST_WRITE_STATUS#:
alu[$SW0, --, B, COMPLETE]	// to indicate it completed the test
alu[$SW1, --, B, A1]

//********************************************************************
// calculate ME (make it between 0-7) and put it into B1
local_csr_rd[active_ctx_sts]
immed[B1, 0]
alu_shf[B1, 0x1f, AND, B1, >>3]
alu[--, B1, -, 0x3]
ble[me0_me3_1#]

alu[B1, 0x3, AND, B1]
alu[B1, 0x4, OR, B1]
br[me_obtain1#]

me0_me3_1#:
alu[B1, 0x3, AND, B1]

me_obtain1#:
//********************************************************************

// XFER REG Test Status reqs 128 locations of Scratch (each thd requires 2)
alu[A1, --, B, A0, <<1]	// thd offset; each thd reqs two locations
alu_shf[A1, A1, OR, B1, <<4] // ME offset; each ME reqs 2*8 = 16 locations
alu[A1, --, B, A1, <<2]	// shifted to access in Lword
scratch[write, $SW0, A1, 0, 2], ctx_swap[scratch_write]

#endif	// XFER_REG_TEST


/************************/
/*		GPR_TEST		*/
/************************/
// Requires 177 uword instructions
// ***** NOTE *****: Assumes GPR A0 works
GPR_TEST#:
#ifdef GPR_TESTS

// ***** Init GPR *****
// Init values for A[x]: A[x] = x
// Init values for B[x]: B[x] = 100 + x
#define_eval X 0
#WHILE(X < 15)
	immed[A/**/X,  X]
	immed[B/**/X, (X + 100)]
	#define_eval X (X + 1)
#ENDLOOP

// ***** Tests All GPRs *****
// Each thread will tests R/W correctness of all 32 of its GPRs
immed[A15, 0]	// Clear A15 to store status of A0-A14 and B0-B14
#define_eval X 0
#WHILE(X < 15)
	alu[A/**/X, A/**/X, +, B/**/X]
	alu[--, A/**/X, -, (100 + X*2)]
	bne[GPR_/**/X/**/_ERROR#]
	alu[B/**/X, A/**/X, +, B/**/X]
	alu[--, B/**/X, -, (200 + X*3)]
	bne[GPR_/**/X/**/_ERROR#]
	GPR_/**/X/**/_CONT#:
	#define_eval X (X+1)
#ENDLOOP

// Transfer status of A0-A14 from A15 to A0 before testing A15
alu[A0, --, B, A15]
// Init values for A15 and B15
immed[A15,  15]
immed[B15, (15 + 100)]

// Test R/ correctness of A15 and B15
alu[A15, A15, +, B15]
alu[--, A15, -, (100 + 15*2)]
bne[GPR_15_ERROR#]
alu[B15, A15, +, B15]
alu[--, B15, -, (200 + 15*3)]
bne[GPR_15_ERROR#]
GPR_15_CONT#:

br[GPR_TEST_WRITE_STATUS#]


// ***** GPR ERROR REPORTING *****
#define_eval X 0
#WHILE(X < 15)
	GPR_/**/X/**/_ERROR#:
	alu_shf[A15, A15, OR, 1, <<X]
	br[GPR_/**/X/**/_CONT#]
	#define_eval X (X + 1)
#ENDLOOP

GPR_15_ERROR#:
alu_shf[A0, A0, OR, 1, <<15]
br[GPR_15_CONT#]

// ***** WRITE STATUS TO SCRATCH *****
GPR_TEST_WRITE_STATUS#:
alu[$SW0, --, B, COMPLETE]	// to indicate it completed the test
alu[$SW1, --, B, A0]

// Obtain ctx number
local_csr_rd[active_ctx_sts]
immed[A0, 0]
alu[A0, 0x7, AND, A0]

//********************************************************************
// calculate ME (make it between 0-7) and put it into B1
local_csr_rd[active_ctx_sts]
immed[B1, 0]
alu_shf[B1, 0x1f, AND, B1, >>3]
alu[--, B1, -, 0x3]
ble[me0_me3_2#]

alu[B1, 0x3, AND, B1]
alu[B1, 0x4, OR, B1]
br[me_obtain2#]

me0_me3_2#:
alu[B1, 0x3, AND, B1]

me_obtain2#:
//********************************************************************

// GPR REG Test Status reqs 128 locations of Scratch (each thd requires 2)