alu[A0, --, B, A0, <<1]	// thd offset; each thd reqs two locations
alu[A0, A0, +, 128]		// Offset; Uses locations 128 - 255 in scratch
alu_shf[A0, A0, OR, B1, <<4] // ME offset; each ME reqs 2*8 = 16 locations
alu[A0, --, B, A0, <<2]	// shifted to access in Lword
scratch[write, $SW0, A0, 0, 2], sig_done[scratch_write]
ctx_arb[scratch_write]

#endif	// GPR_TESTS


/************************/
/*	LOCAL MEMORY TEST	*/
/************************/
/* Flow:	LM0 writes from 0 - 319 and LM1 reads and verify
			Then LM1 writes from 320 - 639 and LM0 reads and verify
*/
// Requires approx. 1964 uword instructions
LOCAL_MEMORY_TEST#:
#ifdef LOCAL_MEM_TEST

br!=ctx[0, END#]
// Initialize the LM address to write to zero
local_csr_wr[ACTIVE_LM_ADDR_0, 0x0]
local_csr_wr[ACTIVE_LM_ADDR_1, 0x0]
nop
nop
nop
// LM0 initialize 0 - 319 of LMA
#define_eval X 0
#WHILE (X < (LM_TO_TEST/2))
	#define_eval X (X + 1)
	immed[*l$index0++, X]
#ENDLOOP

// LM1 reads and verify 0 - 319 LMA
immed[A0, 0]
#define TEMP 0
#define_eval X 0
#WHILE (X < (LM_TO_TEST/2))
	#define_eval X (X + 1)
	#define_eval TEMP (TEMP + X)
	alu[A0, A0, +, *l$index1++]
#ENDLOOP
#if(TEMP > 65535)	// for values that cannot fit into 16 bits
	immed_w1[B0, (TEMP>>16)]
	immed_w0[B0, (TEMP & 0xFFFF)]
#else
	immed[B0, TEMP]
#endif
#undef TEMP
alu[--, A0, -, B0]
bne[LOCAL_MEMORY_ERROR#]

// LM1 initializes 320 - 639
#define_eval X 0
#WHILE (X < (LM_TO_TEST/2))
	#define_eval X (X + 1)
	immed_w1[B0, ((X + LMA_TEST_VAL)>>16)]
	immed_w0[B0, ((X + LMA_TEST_VAL) & 0xFFFF)]
	alu[*l$index1++, --, B, B0]
#ENDLOOP

// LM0 reads and verify 320 - 639 LMA
immed[A0, 0]
#define TEMP 0
#define_eval X 0
#WHILE (X < (LM_TO_TEST/2))
	#define_eval X (X + 1)
	#define_eval TEMP (TEMP + X + LMA_TEST_VAL)
	alu[A0, A0, +, *l$index0++]
#ENDLOOP
#if(TEMP > 65535)	// for values that cannot fit into 16 bits
	immed_w1[B0, (TEMP>>16)]
	immed_w0[B0, (TEMP & 0xFFFF)]
#else
	immed[B0, TEMP]
#endif
#undef TEMP
alu[--, A0, -, B0]
bne[LOCAL_MEMORY_ERROR#]

// test if the ACTIVE_LM_ADDR can be set to point
// to a specified address
immed[A0, ((LM_TO_TEST/4)<<2)]
local_csr_wr[ACTIVE_LM_ADDR_0, A0]
immed[A0, ((LM_TO_TEST/2)<<2)]
local_csr_wr[ACTIVE_LM_ADDR_1, A0]
nop
nop
nop
alu[A0, --, B, *l$index0++]
immed[B0, (LM_TO_TEST/4 + 1)]
alu[--, A0, -, B0]
bne[LOCAL_MEMORY_ERROR#]

alu[A0, --, B, *l$index1++]
immed_w1[B0, ((1 + LMA_TEST_VAL)>>16)]
immed_w0[B0, ((1 + LMA_TEST_VAL) & 0xFFFF)]
alu[--, A0, -, B0]
bne[LOCAL_MEMORY_ERROR#]

immed[A0, PASS]		// indicate a PASS if no errors

LOCAL_MEMORY_ERROR#:
// WRITE STATUS TO SCRATCH
alu[$SW0, --, B, COMPLETE]
alu[$SW1, --, B, A0]		// Status of tests is written

// LMA Test Status reqs 16 locations of Scratch (each ME requires 2)
immed[A0, 256]		// Offset; Uses locations 256 - 271
alu_shf[A0, A0, OR, B1, <<1] // ME offset; each ME reqs 2 locations
alu[A0, --, B, A0, <<2]	// shifted to access in Lword
scratch[write, $SW0, A0, 0, 2], sig_done[scratch_write]
ctx_arb[scratch_write]

#endif


/****************************/
/*	NEXT NEIGHBOR REG TEST	*/
/****************************/
// Requires 424 uword instructions
// ***** NOTE *****: Assumes Interthread signal works
NEXT_NEIGHBOR_REG_TEST#:
#ifdef NEXT_NEIGHBOR_TEST

br!=ctx[0, END#]

// ***** Test for internal NN reg usage *****
// set NN Mode to be FROM THIS MICROENGINE
immed_w1[A0,0x001c]
immed_w0[A0,0xFF00]
local_csr_wr[CTX_Enables,A0]

local_csr_wr[nn_put,0]

// initialize the NN Regs
#define_eval X 0
#WHILE (X < NUM_OF_NN_TO_TEST)
	#define_eval X (X + 1)
	alu[*n$index++, --, B, X]
#ENDLOOP

local_csr_wr[nn_get,0]
nop
nop
nop

immed[A0, 0x2]
#define TEMP 0x2

// Read back the NN Regs
#define_eval X 0
#WHILE (X < NUM_OF_NN_TO_TEST)
	#define_eval X (X + 1)
	#define_eval TEMP (TEMP + X)
	alu[A0, A0, +, *n$index++]
#ENDLOOP

immed[B0, TEMP]
#undef TEMP

alu[--, A0, -, B0]
bne[NEXT_NEIGHBOR_REG_INTERNAL_ERROR#]
immed[A0, COMPLETE]	// to indicate a complete
immed[B0, PASS]		// to indicate a PASS

NEXT_NEIGHBOR_REG_INTERNAL_ERROR#:
// WRITE STATUS TO Scratch
alu[$SW0, --, B, A0]
alu[$SW1, --, B, B0]
// NN Int Test Status reqs 16 locations of Scratch (each ME requires 2)
immed[A0, 288]		// Offset; Uses locations 288 - 303
alu_shf[A0, A0, OR, B1, <<1] // ME offset; each ME reqs 2 locations
alu[A0, --, B, A0, <<2]	// shifted to access in Lword
scratch[write, $SW0, A0, 0, 2], sig_done[scratch_write]
ctx_arb[scratch_write]


// ***** Test for external NN reg usage *****
// Set NN Reg to be used between microengines (requires the usage of inter-threading)
	.sig signal1
	.addr signal1 1
	// set NN Mode to be FROM PREVIOUS NEIGHBOR MICROENGINE
	immed_w1[A1,0x000c]		
	immed_w0[A1,0xFF00]
	local_csr_wr[CTX_Enables,A1]
	local_csr_wr[nn_put,0]
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop

//#if(ME != 0), B1 contains ME number (between 0-7)
alu[--, B1, -, 0]
beq[me0__0#]
	ctx_arb[signal1]

	local_csr_wr[nn_get,0]
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop

	immed[A0, 0]
//	#define TEMP 0
	immed[B0, 0]

	// initialize the NN regs
	#define_eval X 0
	#WHILE (X < NUM_OF_NN_TO_TEST)
		#define_eval X (X + 1)
//		#define_eval TEMP (TEMP + ((ME-1)*128) + X)
		alu[A2, B1, -, 1]
		alu_shf[A2, X, OR, A2, <<7]
		alu[B0, B0, +, A2]
		alu[A0, A0, +, *n$index++]
	#ENDLOOP

//#endif
me0__0#:
	
//#if(ME != 7)	// ME7 has no next external NN reg to generate data
alu[--, B1, -, 0x7]
beq[me7#]
	
	#define_eval X 0
	#WHILE (X < NUM_OF_NN_TO_TEST)
		#define_eval X (X + 1)
//		immed[B2, ((ME*128) + X)]
		alu_shf[B2, X, OR, B1, <<7]
		alu[*n$index++, --, B, B2]
	#ENDLOOP

	// Inter thread (thd 0): ME1 -> ME2 -> ME3 -> ME4 -> ME5 -> ME6 -> ME7
//	#if(ME<3)
	alu[--, B1, -, 0x3]
	bge[me3_me7#]

	alu[B2, B1, +, 0x1]
	alu_shf[B2, 0x1, OR, B2, <<7]
	cap[fast_wr, ALU, interthread_sig]
//	#else
	me3_me7#:
	alu[B2, B1, +, 13]
	alu_shf[B2, 0x1, OR, B2, <<7]
	cap[fast_wr, ALU, interthread_sig]
//	#endif
//#endif
me7#:

//#if(ME != 0)
alu[--, B1, -, 0]
beq[me0__1#]
	alu[--, A0, -, B0]
	bne[NN_EXT_WRITE_STATUS_TO_SCRATCH#]
//#endif
me0__1#:
	immed[A0, PASS]	// to indicate a PASS


NN_EXT_WRITE_STATUS_TO_SCRATCH#:
// WRITE STATUS TO Scratch
immed[$SW0, COMPLETE]	// to indicate it completed the test
alu[$SW1, --, B, A0]
// NN Ext Test Status reqs 16 locations of Scratch (each ME requires 2)
immed[A0, 304]		// Offset; Uses locations 304 - 319
alu_shf[A0, A0, OR, B1, <<1] // ME offset; each ME reqs 2 locations
alu[A0, --, B, A0, <<2]	// shifted to access in Lword
scratch[write, $SW0, A0, 0, 2], sig_done[scratch_write]
ctx_arb[scratch_write]

#endif	// NEXT_NEIGHBOR_TEST


END#:
nop
nop
nop
nop
ctx_arb[kill]
nop
nop
nop
nop
nop
nop
nop
nop