?? _primary.vhd
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library verilog;use verilog.vl_types.all;entity iir_6_filter is port( din : in vl_logic_vector(17 downto 0); dout : out vl_logic_vector(17 downto 0); clk : in vl_logic; fltsel : in vl_logic; ce_50k : in vl_logic; ce_25k : in vl_logic; rstn : in vl_logic );end iir_6_filter;
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