#define GSYNC_OFF           0x00     /* CLKG always running                   */
#define GSYNC_ON            0x01     /* CLKG and FSG synch'ed to FSR          */ 


/* Multi-channel Control Register 1 and 2 MCR1/2 */

#define RMCM_CHANNEL_ENABLE	0x00 	 /* all 128 channels enabled              */
#define RMCM_CHANNEL_DISABLE	0x01 	 /* all channels disabled, selected by    */
						 /* enabling RP(A/B)BLK, RCER(A/B)        */

#define XMCM_CHANNEL_DX_DRIVEN 0x00  /* transmit data over DX pin for as many */
						 /* number of words as required           */
#define XMCM_XCER_CHAN_TO_DXR	0x01 	 /* selected channels written to DXR      */
#define XMCM_ALL_WORDS_TO_DXR	0x02 	 /* all words copied to DXR(1/2),         */
						 /* DX only driven for selected words     */
#define XMCM_CHANNEL_SYM_R/X	0x03 	 /* symmetric transmit and receive        */
						 /* operation                             */
     


#ifdef _INLINE
#define __INLINE static inline
#else
#define __INLINE
#endif

/********* Macro Definitions **************************************/


/******************************************************************/
/* MCBSP_BYTES_PER_WORD - return # of bytes required to hold #    */
/*                        of bits indicated by wdlen              */
/******************************************************************/
#define MCBSP_BYTES_PER_WORD(wdlen) \
        ((int)((wdlen) + 1) / 2)

/******************************************************************/
/* MCBSP_ENABLE(unsigned short port_no, unsigned short type) -    */
/*            starts serial port receive and/or transmit          */
/*            type= 1 rx, type= 2 tx, type= 3 both                */
/******************************************************************/
#define MCBSP_ENABLE(port_no,mode) \
         REG_WRITE(SPCR1_ADDR(port_no), \
          (MCBSP_SUBREG_READ(port_no, SPCR1_SUBADDR) | (mode & 1))); \
         REG_WRITE(SPCR2_ADDR(port_no), \
          (MCBSP_SUBREG_READ(port_no, SPCR2_SUBADDR) | ((mode >> 1) & 1)))

/******************************************************************/
/* MCBSP_TX_RESET() - reset transmit side of serial port          */
/*                                                                */
/******************************************************************/
#define MCBSP_TX_RESET(port_no)\
        MCBSP_SUBREG_BITWRITE(port_no, SPCR2_SUBADDR, XRST, XRST_SZ, 0);
  

/******************************************************************/
/* MCBSP_RX_RESET() - reset receive side of serial port           */
/*                                                                */
/******************************************************************/
#define MCBSP_RX_RESET(port_no)\
	  MCBSP_SUBREG_BITWRITE(port_no, SPCR1_SUBADDR, RRST, RRST_SZ, 0);
  

/******************************************************************/
/* MCBSP_DRR1_READ() - read data value from serial port           */
/******************************************************************/
/* use instead: MCBSP_SUBREG_READ(... , DRR1_SUBADDR, ... )*/
  

/******************************************************************/
/* MCBSP_DRR2_READ() - read data value from serial port           */
/******************************************************************/
/* use instead: MCBSP_SUBREG_READ(... , DRR2_SUBADDR, ... )*/

                       

/******************************************************************/
/* MCBSP_DRR12_READ() - read data value from serial port          */
/*                      return value as unsigned long             */
/******************************************************************/
#define MCBSP_DRR12_READ(port_no)\
     (((*(volatile unsigned long* DRR2_ADDR(port_no)))<<16) &\
      (REG_READ(DRR1_ADDR(port_no)))
                            

/******************************************************************/
/* MCBSP_DXR12_WRITE() - write data value to serial port          */
/******************************************************************/
#define MCBSP_DXR12_WRITE(port_no, value)\
     (REG_WRITE(DXR2_ADDR(port_no), (unsigned int) (value >> 16)),\
      (REG_WRITE(DXR1_ADDR(port_no), (unsigned int) value)) )
     

/******************************************************************/
/* MCBSP_IO_ENABLE() - place port in general purpose I/O mode     */
/******************************************************************/
#define MCBSP_IO_ENABLE(port_no) \
        { MCBSP_TX_RESET(port_no); MCBSP_RX_RESET(port_no); \
          MCBSP_SUBREG_BITWRITE(port_no, PCR_SUBADDR, RIOEN, 2, 0x0003) } 


/******************************************************************/
/* MCBSP_IO_DISABLE() - take port out of general purpose I/O mode */
/******************************************************************/
#define MCBSP_IO_DISABLE(port_no) \
        MCBSP_SUBREG_BITWRITE(port_no, PCR_SUBADDR, RIOEN, 2, 0x0000)


/******************************************************************/
/* MCBSP_FRAME_SYNC_ENABLE - sets FRST bit in SPCR                */
/******************************************************************/
#define MCBSP_FRAME_SYNC_ENABLE(port_no) \
        MCBSP_SUBREG_BITWRITE(port_no, SPCR2_SUBADDR, FRST, FRST_SZ, 0x0001)


/******************************************************************/
/* MCBSP_FRAME_SYNC_RESET - clrs FRST bit in SPCR                 */
/******************************************************************/
#define MCBSP_FRAME_SYNC_RESET(port_no) \
        MCBSP_SUBREG_BITWRITE(port_no, SPCR2_SUBADDR, FRST, FRST_SZ, 0x0000)


/******************************************************************/
/* MCBSP_SAMPLE_RATE_ENABLE - sets GRST bit in SPCR               */
/******************************************************************/
#define MCBSP_SAMPLE_RATE_ENABLE(port_no) \
        MCBSP_SUBREG_BITWRITE(port_no, SPCR2_SUBADDR, GRST, GRST_SZ, 0x0001)


/******************************************************************/
/* MCBSP_SAMPLE_RATE_RESET - clrs GRST bit in SPCR                */
/******************************************************************/
#define MCBSP_SAMPLE_RATE_RESET(port_no) \
        MCBSP_SUBREG_BITWRITE(port_no, SPCR2_SUBADDR, GRST, GRST_SZ, 0x0000)


/******************************************************************/
/* MCBSP_RRDY - returns selected ports RRDY                       */
/******************************************************************/
#define MCBSP_RRDY(port_no) \
        MCBSP_SUBREG_BITREAD(port_no, SPCR1_SUBADDR, RRDY, RRDY_SZ)
        
/******************************************************************/
/* MCBSP_XRDY - returns selected ports XRDY                       */
/******************************************************************/
#define MCBSP_XRDY(port_no) \
        MCBSP_SUBREG_BITREAD(port_no, SPCR2_SUBADDR, XRDY, XRDY_SZ)


/******************************************************************/
/* MCBSP_LOOPBACK_ENABLE - places selected port in loopback       */
/******************************************************************/
#define MCBSP_LOOPBACK_ENABLE(port_no) \
        MCBSP_SUBREG_BITWRITE(port_no, SPCR1_SUBADDR, DLB, DLB_SZ, 0x0001)


/******************************************************************/
/* MCBSP_LOOPBACK_DISABLE - takes port out of DLB                 */
/******************************************************************/
#define MCBSP_LOOPBACK_DISABLE(port_no) \
        MCBSP_SUBREG_BITWRITE(port_no, SPCR1_SUBADDR, DLB, DLB_SZ, 0x0000)


#ifdef __INLINE
#undef __INLINE
#endif

#endif /*_MCBSP_H_*/