#include "DSP28_Device.h"
#include "extern_ram.h"
#include "string.h"

extern unsigned int RamH0Funcs_loadstart;
extern unsigned int RamH0Funcs_loadend;
extern unsigned int RamH0Funcs_runstart;

extern unsigned int RamL0L1Funcs_loadstart;
extern unsigned int RamL0L1Funcs_loadend;
extern unsigned int RamL0L1Funcs_runstart;
/*
extern unsigned int cinit_loadstart;
extern unsigned int cinit_loadend;
extern unsigned int cinit_runstart;

extern unsigned int text_loadstart;
extern unsigned int text_loadend;
extern unsigned int text_runstart;
*/
/*
#pragma CODE_SECTION(InitFlash, "RamH0Funcs")
void InitFlash(void);

#pragma CODE_SECTION(xcorr, "RamL0L1Funcs")
unsigned long xcorr(const long add_id1,const long add_id2,long datalen);
*/
unsigned int		a1[16];
//unsigned int		ram_data[3700];
unsigned long       ram_add0=0,ram_add1=0,ram_add2=0,ram_add3=0,l,k,rd_cnt,m;
unsigned int a2=0;
int wr_flag;
#define sample_length 2000
//const long sample_length = 32768;
//const long uart_length = 16383;
const long one_sector_add = 16383;
const long two_sector_add = 32767;
const long three_sector_add = 49151;
float	adclo=0.0;
int i,j;
unsigned int data1,data2;
char data3,data4;

// Prototype statements for functions found within this file.
interrupt void ad(void);
void dly(unsigned long cnt);
unsigned long xcorr(const long add_id1,const long add_id2,long datalen);
void main(void)
{
	//unsigned int x1[16384],x2[16384];

	memcpy(&RamH0Funcs_runstart,
		   &RamH0Funcs_loadstart,
		   &RamH0Funcs_loadend - &RamH0Funcs_loadstart);
		   
	InitFlash();
	
	memcpy(&RamL0L1Funcs_runstart,
		   &RamL0L1Funcs_loadstart,
		   &RamL0L1Funcs_loadend - &RamL0L1Funcs_loadstart);

/*	
	memcpy(&cinit_runstart,
       	   &cinit_loadstart,
           &cinit_loadend-&cinit_loadstart
           );
	
	memcpy(&text_runstart,
       	   &text_loadstart,
           &text_loadend-&text_loadstart);
*/
         
	InitSysCtrl();

	DINT;
	IER = 0x0000;
	IFR = 0x0000;

	InitPieCtrl();


	InitPieVectTable();	
	
	EALLOW;	// This is needed to write to EALLOW protected registers
	PieVectTable.ADCINT=&ad;
	EDIS;   // This is needed to disable write to EALLOW protected registers
    
    InitAdc();
    InitSci();

    // Enable INT14 which is connected to CPU-Timer 2:
	IER |= M_INT1;
	//KickDog();
    // Enable global Interrupts and higher priority real-time debug events:
	
	EINT;   // Enable Maskable interrupt INTM
	ERTM;	// Enable Global realtime interrupt DBGM
	while(AdcRegs.ADC_ST_FLAG.bit.SEQ1_BSY==0)
	{			

		AdcRegs.ADCTRL2.bit.SOC_SEQ1=1;

	}

	m = 0;
	wr_flag = 1;
	ram_add0 = 0;
	while(wr_flag == 1.0);
	//rd_cnt = sample_length/uart_length;
	ram_add0 = 0;
	ram_add1 = 0;
	ram_add2 = 0;
	ram_add3 = 0;
					
 	data2 = xcorr(0,one_sector_add,sample_length);
 	
 	data3=(data2>>4) & 0xff;
	data4=((data2>>4) & 0xff00)>>8;
	while(!SciaRegs.SCICTL2.bit.TXRDY);
	SciaRegs.SCITXBUF = data3;
	while(!SciaRegs.SCICTL2.bit.TXRDY);
	SciaRegs.SCITXBUF = data4;
/*
 	xcorr(0,two_sector_add,sample_length);		
  
	xcorr(0,three_sector_add,sample_length);		
  
	xcorr(one_sector_add,three_sector_add,sample_length);				
*/	
	while(1);
} 	


interrupt void ad(void)
{
	IFR=0x0000;
//	PieCtrl.PIEIFR1.all = 0;
	PieCtrl.PIEACK.all=0xffff;
	a2++;

	a1[0]=AdcRegs.RESULT0;
	a1[1]=AdcRegs.RESULT1;
	a1[2]=AdcRegs.RESULT2;
	a1[3]=AdcRegs.RESULT3;
// store the first channel data to RAM	
	data1 = a1[0];
	//data1=(a1[i]>>4) & 0xff;
	//data2=((a1[i]>>4) & 0xff00)>>8;
	*(EXT_RAM + ram_add0) = data1;
	//if(*(EXT_RAM + ram_add0) != data1)
	//{
		//while(1);
	//}
	ram_add0 = ram_add0 + 1;
// store the second channel data to RAM		
	data1 = a1[1];
	//data1=(a1[i]>>4) & 0xff;
	//data2=((a1[i]>>4) & 0xff00)>>8;
	*(EXT_RAM + one_sector_add + ram_add1) = data1;
	//if(*(EXT_RAM + one_sector_add + ram_add1) != data1)
	//{
		//while(1);
	//}
	ram_add1 = ram_add1 + 1;
// store the third channel data to RAM		
	data1 = a1[2];
	//data1=(a1[i]>>4) & 0xff;
	//data2=((a1[i]>>4) & 0xff00)>>8;
	*(EXT_RAM + two_sector_add + ram_add2) = data1;
	//if(*(EXT_RAM + two_sector_add + ram_add2) != data1)
	//{
		//while(1);
	//}
	ram_add2 = ram_add2 + 1;
// store the fourth channel data to RAM		
	data1 = a1[3];
	//data1=(a1[i]>>4) & 0xff;
	//data2=((a1[i]>>4) & 0xff00)>>8;
	*(EXT_RAM + three_sector_add + ram_add3) = data1;
	//if(*(EXT_RAM + three_sector_add + ram_add3) != data1)
	//{
		//while(1);
	//}
	ram_add3 = ram_add3 + 1;
			
	AdcRegs.ADC_ST_FLAG.bit.INT_SEQ1_CLR=1;
	AdcRegs.ADCTRL2.bit.RST_SEQ1=1;
	AdcRegs.ADCTRL2.bit.SOC_SEQ1=1;
	
	if(ram_add0 > sample_length-1)
	{
		wr_flag = 0;
		AdcRegs.ADCTRL2.bit.SOC_SEQ1=0;
		AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1=0;
	}
	EINT;	
	
}

void dly(unsigned long cnt)
{
	int k;
	for(k=0;k<cnt;k++);
}

/*
unsigned long corr(unsigned int x[sample_length],unsigned int y[sample_length],unsigned long datalen)
{
	unsigned long mx,my;
	unsigned long xc_max,xc_max_id,sxy;
	unsigned long maxdelay,delay;
	datalen = 2;	
	mx = 0;
 	my = 0;   
 	for (i=0;i<sample_length;i++)
 	{
    	mx += x[i];
    	my += y[i];
     	//mx3 += x3[i];
     	//mx4 += x5[i];
    }
 	mx /= datalen;
   	my /= datalen;

 
    // Calculate the correlation series 
   	xc_max=0;
   	xc_max_id=0;
   	maxdelay=datalen;
   	for (delay=-maxdelay;delay<maxdelay;delay++) 
	{
    	sxy = 0;
      	for (i=0;i<datalen;i++)
	  	{
        	j = i + delay;
         	if (j < 0 || j >= datalen)
            	continue;
         	else
            	sxy += (x[i] - mx) * (y[j] - my);
      	}
     
      	if(xc_max<sxy)
      	{
	      	xc_max=sxy;
	      	xc_max_id=delay;
	  	}
      
   	} 
   	return xc_max_id;
 }  
 */
 		
unsigned long xcorr(const long add_id1,const long add_id2,long datalen)
{   
   int x,y;
   long i,j;
   long xc_max_id,delay,maxdelay;
   double xc_max;
   double mx,my,sx,sy,sxy,denom;
	
   /* Calculate the mean of the two series x[], y[] */
   mx = 0;
   my = 0; 
   for (i=0;i<datalen;i++) {
      //mx += x[i];
      //my += y[i];      
      x = *(EXT_RAM + add_id1 + i);   
      y = *(EXT_RAM + add_id2 + i);
      mx += x;
      my += y;
   }
   mx /= datalen;
   my /= datalen;

   /* Calculate the denominator */
 
    /* Calculate the correlation series */
   xc_max=0;
   xc_max_id=0;
   maxdelay=datalen;
   for (delay=-maxdelay;delay<maxdelay;delay++) 
	{
      sxy = 0;
      for (i=0;i<datalen;i++)
	  {
         j = i + delay;
         if (j < 0 || j >= datalen)
            continue;
         else
            //sxy += (x[i] - mx) * (y[j] - my);
            x = *(EXT_RAM + add_id1 + i);
            y = *(EXT_RAM + add_id2 + j);
            sxy += (x-mx) * (y-my);
      }
     
      if(xc_max<sxy)
      {
	      xc_max=sxy;
	      xc_max_id=delay;
	  }
      
   } 
   return xc_max_id;  
}

void InitFlash(void)
{
	//asm("EALLOW"); // Enable EALLOW protected register access
	EALLOW;
	FlashRegs.FPWR.bit.PWR = 3; // Flash set to active mode
	FlashRegs.FSTATUS.bit.V3STAT = 1; // Clear the 3VSTAT bit
	FlashRegs.FSTDBYWAIT.bit.STDBYWAIT = 0x01FF; // Sleep to standby cycles
	FlashRegs.FACTIVEWAIT.bit.ACTIVEWAIT = 0x01FF; // Standby to active cycles
	FlashRegs.FBANKWAIT.bit.RANDWAIT = 5; // Random access waitstates
	FlashRegs.FBANKWAIT.bit.PAGEWAIT = 5; // Paged access waitstates
	FlashRegs.FOTPWAIT.bit.OTPWAIT = 5; // Random access waitstates
	FlashRegs.FOPT.bit.ENPIPE = 1; // Enable the flash pipeline
	//asm("EDIS"); // Disable EALLOW protected register access
	EDIS;
	asm(" RPT #6 || NOP");

}

//===========================================================================
// No more.
//===========================================================================