/* Machine-dependent ELF dynamic relocation inline functions.  Sparc64 version.   Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006	Free Software Foundation, Inc.   This file is part of the GNU C Library.   The GNU C Library is free software; you can redistribute it and/or   modify it under the terms of the GNU Lesser General Public   License as published by the Free Software Foundation; either   version 2.1 of the License, or (at your option) any later version.   The GNU C Library is distributed in the hope that it will be useful,   but WITHOUT ANY WARRANTY; without even the implied warranty of   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU   Lesser General Public License for more details.   You should have received a copy of the GNU Lesser General Public   License along with the GNU C Library; if not, write to the Free   Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA   02111-1307 USA.  */#ifndef dl_machine_h#define dl_machine_h#define ELF_MACHINE_NAME "sparc64"#include <string.h>#include <sys/param.h>#include <ldsodefs.h>#include <sysdep.h>#ifndef VALIDX# define VALIDX(tag) (DT_NUM + DT_THISPROCNUM + DT_VERSIONTAGNUM \		      + DT_EXTRANUM + DT_VALTAGIDX (tag))#endif#define ELF64_R_TYPE_ID(info)	((info) & 0xff)#define ELF64_R_TYPE_DATA(info) ((info) >> 8)/* Return nonzero iff ELF header is compatible with the running host.  */static inline intelf_machine_matches_host (const Elf64_Ehdr *ehdr){  return ehdr->e_machine == EM_SPARCV9;}/* We have to do this because elf_machine_{dynamic,load_address} can be   invoked from functions that have no GOT references, and thus the compiler   has no obligation to load the PIC register.  */#define LOAD_PIC_REG(PIC_REG)	\do {	Elf64_Addr tmp;		\	__asm("sethi %%hi(_GLOBAL_OFFSET_TABLE_-4), %1\n\t" \	      "rd %%pc, %0\n\t" \	      "add %1, %%lo(_GLOBAL_OFFSET_TABLE_+4), %1\n\t" \	      "add %0, %1, %0" \	      : "=r" (PIC_REG), "=r" (tmp)); \} while (0)/* Return the link-time address of _DYNAMIC.  Conveniently, this is the   first element of the GOT.  This must be inlined in a function which   uses global data.  */static inline Elf64_Addrelf_machine_dynamic (void){  register Elf64_Addr *elf_pic_register __asm__("%l7");  LOAD_PIC_REG (elf_pic_register);  return *elf_pic_register;}/* Return the run-time load address of the shared object.  */static inline Elf64_Addrelf_machine_load_address (void){  register Elf32_Addr *pc __asm ("%o7");  register Elf64_Addr *got __asm ("%l7");  __asm ("sethi %%hi(_GLOBAL_OFFSET_TABLE_-4), %1\n\t"         "call 1f\n\t"         " add %1, %%lo(_GLOBAL_OFFSET_TABLE_+4), %1\n\t"         "call _DYNAMIC\n\t"         "call _GLOBAL_OFFSET_TABLE_\n"         "1:\tadd %1, %0, %1\n\t" : "=r" (pc), "=r" (got));  /* got is now l_addr + _GLOBAL_OFFSET_TABLE_     *got is _DYNAMIC     pc[2]*4 is l_addr + _DYNAMIC - (long)pc - 8     pc[3]*4 is l_addr + _GLOBAL_OFFSET_TABLE_ - (long)pc - 12  */  return (Elf64_Addr) got - *got + (Elf32_Sword) ((pc[2] - pc[3]) * 4) - 4;}/* We have 4 cases to handle.  And we code different code sequences   for each one.  I love V9 code models...  */static inline void __attribute__ ((always_inline))sparc64_fixup_plt (struct link_map *map, const Elf64_Rela *reloc,		   Elf64_Addr *reloc_addr, Elf64_Addr value,		   Elf64_Addr high, int t){  unsigned int *insns = (unsigned int *) reloc_addr;  Elf64_Addr plt_vaddr = (Elf64_Addr) reloc_addr;  Elf64_Sxword disp = value - plt_vaddr;  /* Now move plt_vaddr up to the call instruction.  */  plt_vaddr += ((t + 1) * 4);  /* PLT entries .PLT32768 and above look always the same.  */  if (__builtin_expect (high, 0) != 0)    {      *reloc_addr = value - map->l_addr;    }  /* Near destination.  */  else if (disp >= -0x800000 && disp < 0x800000)    {      /* As this is just one instruction, it is thread safe and so	 we can avoid the unnecessary sethi FOO, %g1.	 b,a target  */      insns[0] = 0x30800000 | ((disp >> 2) & 0x3fffff);      __asm __volatile ("flush %0" : : "r" (insns));    }  /* 32-bit Sparc style, the target is in the lower 32-bits of     address space.  */  else if (insns += t, (value >> 32) == 0)    {      /* sethi	%hi(target), %g1	 jmpl	%g1 + %lo(target), %g0  */      insns[1] = 0x81c06000 | (value & 0x3ff);      __asm __volatile ("flush %0 + 4" : : "r" (insns));      insns[0] = 0x03000000 | ((unsigned int)(value >> 10));      __asm __volatile ("flush %0" : : "r" (insns));    }  /* We can also get somewhat simple sequences if the distance between     the target and the PLT entry is within +/- 2GB.  */  else if ((plt_vaddr > value	    && ((plt_vaddr - value) >> 31) == 0)	   || (value > plt_vaddr	       && ((value - plt_vaddr) >> 31) == 0))    {      unsigned int displacement;      if (plt_vaddr > value)	displacement = (0 - (plt_vaddr - value));      else	displacement = value - plt_vaddr;      /* mov	%o7, %g1	 call	displacement	  mov	%g1, %o7  */      insns[2] = 0x9e100001;      __asm __volatile ("flush %0 + 8" : : "r" (insns));      insns[1] = 0x40000000 | (displacement >> 2);      __asm __volatile ("flush %0 + 4" : : "r" (insns));      insns[0] = 0x8210000f;      __asm __volatile ("flush %0" : : "r" (insns));    }  /* Worst case, ho hum...  */  else    {      unsigned int high32 = (value >> 32);      unsigned int low32 = (unsigned int) value;      /* ??? Some tricks can be stolen from the sparc64 egcs backend	     constant formation code I wrote.  -DaveM  */      if (__builtin_expect (high32 & 0x3ff, 0))	{	  /* sethi	%hh(value), %g1	     sethi	%lm(value), %g5	     or		%g1, %hm(value), %g1	     or		%g5, %lo(value), %g5	     sllx	%g1, 32, %g1	     jmpl	%g1 + %g5, %g0	      nop  */	  insns[5] = 0x81c04005;	  __asm __volatile ("flush %0 + 20" : : "r" (insns));	  insns[4] = 0x83287020;	  __asm __volatile ("flush %0 + 16" : : "r" (insns));	  insns[3] = 0x8a116000 | (low32 & 0x3ff);	  __asm __volatile ("flush %0 + 12" : : "r" (insns));	  insns[2] = 0x82106000 | (high32 & 0x3ff);	}      else	{	  /* sethi	%hh(value), %g1	     sethi	%lm(value), %g5	     sllx	%g1, 32, %g1	     or		%g5, %lo(value), %g5	     jmpl	%g1 + %g5, %g0	      nop  */	  insns[4] = 0x81c04005;	  __asm __volatile ("flush %0 + 16" : : "r" (insns));	  insns[3] = 0x8a116000 | (low32 & 0x3ff);	  __asm __volatile ("flush %0 + 12" : : "r" (insns));	  insns[2] = 0x83287020;	}      __asm __volatile ("flush %0 + 8" : : "r" (insns));      insns[1] = 0x0b000000 | (low32 >> 10);      __asm __volatile ("flush %0 + 4" : : "r" (insns));      insns[0] = 0x03000000 | (high32 >> 10);      __asm __volatile ("flush %0" : : "r" (insns));    }}static inline Elf64_Addr __attribute__ ((always_inline))elf_machine_fixup_plt (struct link_map *map, lookup_t t,		       const Elf64_Rela *reloc,		       Elf64_Addr *reloc_addr, Elf64_Addr value){  sparc64_fixup_plt (map, reloc, reloc_addr, value + reloc->r_addend,		     reloc->r_addend, 1);  return value;}/* Return the final value of a plt relocation.  */static inline Elf64_Addrelf_machine_plt_value (struct link_map *map, const Elf64_Rela *reloc,		       Elf64_Addr value){  /* Don't add addend here, but in elf_machine_fixup_plt instead.     value + reloc->r_addend is the value which should actually be     stored into .plt data slot.  */  return value;}/* ELF_RTYPE_CLASS_PLT iff TYPE describes relocation of a PLT entry, so   PLT entries should not be allowed to define the value.   ELF_RTYPE_CLASS_NOCOPY iff TYPE should not be allowed to resolve to one   of the main executable's symbols, as for a COPY reloc.  */#if !defined RTLD_BOOTSTRAP || USE___THREAD# define elf_machine_type_class(type) \  ((((type) == R_SPARC_JMP_SLOT						      \     || ((type) >= R_SPARC_TLS_GD_HI22 && (type) <= R_SPARC_TLS_TPOFF64))     \    * ELF_RTYPE_CLASS_PLT)						      \   | (((type) == R_SPARC_COPY) * ELF_RTYPE_CLASS_COPY))#else# define elf_machine_type_class(type) \  ((((type) == R_SPARC_JMP_SLOT) * ELF_RTYPE_CLASS_PLT)	\   | (((type) == R_SPARC_COPY) * ELF_RTYPE_CLASS_COPY))#endif/* A reloc type used for ld.so cmdline arg lookups to reject PLT entries.  */#define ELF_MACHINE_JMP_SLOT	R_SPARC_JMP_SLOT/* The SPARC never uses Elf64_Rel relocations.  */#define ELF_MACHINE_NO_REL 1/* The SPARC overlaps DT_RELA and DT_PLTREL.  */#define ELF_MACHINE_PLTREL_OVERLAP 1/* Set up the loaded object described by L so its unrelocated PLT   entries will jump to the on-demand fixup code in dl-runtime.c.  */static inline intelf_machine_runtime_setup (struct link_map *l, int lazy, int profile){  if (l->l_info[DT_JMPREL] && lazy)    {      extern void _dl_runtime_resolve_0 (void);      extern void _dl_runtime_resolve_1 (void);      extern void _dl_runtime_profile_0 (void);      extern void _dl_runtime_profile_1 (void);      Elf64_Addr res0_addr, res1_addr;      unsigned int *plt = (void *) D_PTR (l, l_info[DT_PLTGOT]);      if (__builtin_expect(profile, 0))	{	  res0_addr = (Elf64_Addr) &_dl_runtime_profile_0;	  res1_addr = (Elf64_Addr) &_dl_runtime_profile_1;	  if (GLRO(dl_profile) != NULL	      && _dl_name_match_p (GLRO(dl_profile), l))	    GL(dl_profile_map) = l;	}      else	{	  res0_addr = (Elf64_Addr) &_dl_runtime_resolve_0;	  res1_addr = (Elf64_Addr) &_dl_runtime_resolve_1;	}      /* PLT0 looks like:         sethi	%uhi(_dl_runtime_{resolve,profile}_0), %g4	 sethi	%hi(_dl_runtime_{resolve,profile}_0), %g5	 or	%g4, %ulo(_dl_runtime_{resolve,profile}_0), %g4	 or	%g5, %lo(_dl_runtime_{resolve,profile}_0), %g5	 sllx	%g4, 32, %g4	 add	%g4, %g5, %g5	 jmpl	%g5, %g4	  nop       */      plt[0] = 0x09000000 | (res0_addr >> (64 - 22));      plt[1] = 0x0b000000 | ((res0_addr >> 10) & 0x003fffff);      plt[2] = 0x88112000 | ((res0_addr >> 32) & 0x3ff);      plt[3] = 0x8a116000 | (res0_addr & 0x3ff);      plt[4] = 0x89293020;      plt[5] = 0x8a010005;      plt[6] = 0x89c14000;      plt[7] = 0x01000000;      /* PLT1 looks like:         sethi	%uhi(_dl_runtime_{resolve,profile}_1), %g4	 sethi	%hi(_dl_runtime_{resolve,profile}_1), %g5	 or	%g4, %ulo(_dl_runtime_{resolve,profile}_1), %g4	 or	%g5, %lo(_dl_runtime_{resolve,profile}_1), %g5	 sllx	%g4, 32, %g4	 add	%g4, %g5, %g5	 jmpl	%g5, %g4	  nop       */      plt[8] = 0x09000000 | (res1_addr >> (64 - 22));      plt[9] = 0x0b000000 | ((res1_addr >> 10) & 0x003fffff);      plt[10] = 0x88112000 | ((res1_addr >> 32) & 0x3ff);      plt[11] = 0x8a116000 | (res1_addr & 0x3ff);      plt[12] = 0x89293020;      plt[13] = 0x8a010005;      plt[14] = 0x89c14000;      plt[15] = 0x01000000;      /* Now put the magic cookie at the beginning of .PLT2	 Entry .PLT3 is unused by this implementation.  */      *((struct link_map **)(&plt[16])) = l;      if (__builtin_expect (l->l_info[VALIDX(DT_GNU_PRELINKED)] != NULL, 0)	  || __builtin_expect (l->l_info [VALIDX (DT_GNU_LIBLISTSZ)] != NULL, 0))	{	  /* Need to reinitialize .plt to undo prelinking.  */	  Elf64_Rela *rela = (Elf64_Rela *) D_PTR (l, l_info[DT_JMPREL]);	  Elf64_Rela *relaend	    = (Elf64_Rela *) ((char *) rela			      + l->l_info[DT_PLTRELSZ]->d_un.d_val);	  /* prelink must ensure there are no R_SPARC_NONE relocs left	     in .rela.plt.  */	  while (rela < relaend)	    {	      if (__builtin_expect (rela->r_addend, 0) != 0)		{                  Elf64_Addr slot = ((rela->r_offset + 0x400				      - (Elf64_Addr) plt)				     / 0x1400) * 0x1400				    + (Elf64_Addr) plt - 0x400;		  /* ldx [%o7 + X], %g1  */		  unsigned int first_ldx = *(unsigned int *)(slot + 12);		  Elf64_Addr ptr = slot + (first_ldx & 0xfff) + 4;		  *(Elf64_Addr *) rela->r_offset		    = (Elf64_Addr) plt		      - (slot + ((rela->r_offset - ptr) / 8) * 24 + 4);		  ++rela;		  continue;		}	      *(unsigned int *) rela->r_offset		= 0x03000000 | (rela->r_offset - (Elf64_Addr) plt);	      *(unsigned int *) (rela->r_offset + 4)		= 0x30680000 | ((((Elf64_Addr) plt + 32				  - rela->r_offset - 4) >> 2) & 0x7ffff);	      __asm __volatile ("flush %0" : : "r" (rela->r_offset));	      __asm __volatile ("flush %0+4" : : "r" (rela->r_offset));	      ++rela;	    }	}    }  return lazy;}/* The PLT uses Elf64_Rela relocs.  */#define elf_machine_relplt elf_machine_rela