EDA Netlist Writer report for myadder
Mon Jul 23 13:40:32 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
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  1. Legal Notice
  2. EDA Netlist Writer Summary
  3. Simulation Settings
  4. Simulation Generated Files
  5. EDA Netlist Writer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------+
; EDA Netlist Writer Summary                                        ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Mon Jul 23 13:40:32 2007 ;
; Revision Name             ; myadder                               ;
; Top-level Entity Name     ; adder4                                ;
; Family                    ; Cyclone                               ;
; Simulation Files Creation ; Successful                            ;
+---------------------------+---------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Simulation Settings                                                                                             ;
+--------------------------------------------------------------------------------------------+--------------------+
; Option                                                                                     ; Setting            ;
+--------------------------------------------------------------------------------------------+--------------------+
; Tool Name                                                                                  ; ModelSim (Verilog) ;
; Generate netlist for functional simulation only                                            ; Off                ;
; Time scale                                                                                 ; 1 ps               ;
; Truncate long hierarchy paths                                                              ; Off                ;
; Map illegal HDL characters                                                                 ; Off                ;
; Flatten buses into individual nodes                                                        ; Off                ;
; Maintain hierarchy                                                                         ; Off                ;
; Bring out device-wide set/reset signals as ports                                           ; Off                ;
; Enable glitch filtering                                                                    ; Off                ;
; Do not write top level VHDL entity                                                         ; Off                ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off                ;
; Architecture name in VHDL output netlist                                                   ; structure          ;
+--------------------------------------------------------------------------------------------+--------------------+


+---------------------------------------------------------+
; Simulation Generated Files                              ;
+---------------------------------------------------------+
; Generated Files                                         ;
+---------------------------------------------------------+
; D:/program/FPGA/adder/simulation/modelsim/myadder.vo    ;
; D:/program/FPGA/adder/simulation/modelsim/myadder_v.sdo ;
+---------------------------------------------------------+


+-----------------------------+
; EDA Netlist Writer Messages ;
+-----------------------------+
Info: *******************************************************************
Info: Running Quartus II EDA Netlist Writer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Mon Jul 23 13:40:30 2007
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off myadder -c myadder
Info: Generated files "myadder.vo" and "myadder_v.sdo" in directory "D:/program/FPGA/adder/simulation/modelsim/" for EDA simulation tool
Info: Quartus II EDA Netlist Writer was successful. 0 errors, 0 warnings
    Info: Processing ended: Mon Jul 23 13:40:32 2007
    Info: Elapsed time: 00:00:02