<br>
        Table 1. Allan Intercept
        <p>A more careful examination of the particular nanosecond kernel used for case (2) reveals an interesting and important design issue. Recent Intel chipsets have provisions for a system management interrupt (SMI), which implements the automatic power management (APM) features and monitors temperature, voltages and fans. In general, the SMI is not controllable by the BIOS and must be enabled by a specific register. The effect of the SMI on the Allan deviation is shown in Figure 2. If the SMI is enabled, the upper trace results; if disabled, the lower trace results. Obviously, the SMI has a significant affect on timekeeping performance.</p>
        <p>The result of the SMI on system timekeeping is shown in Figures 3 and 4. Figure 3 shows the phase offset with SMI disabled over a 1000 s interval, while Figure 4 shows the offset with SMI enabled over the same interval. The problem is immediately apparent as the occurrence of 50-<font face="symbol">m</font>s spikes at apparent intervals of about 250 s. The amplitude of the spikes represent the time in the SMI context. However, the actual interrupt rate cannot be directly determined, as the figure actually shows only the beat frequency against the PPS signal. There is no immediate explanation whether these spikes occur in other contexts or whether they occur with other chipsets. Apparently, some chipsets make better timekeepers than others.</p>
        <table width="100%" cols="1">
            <tr>
                <td align="center"><img src="pic/DM40_tg.gif" alt="gif"></td>
                <td align="center"><img src="pic/DM30_tg.gif" alt="gif"></td>
            </tr>
            <tr>
                <td align="center">Figure 3. Phase Offset of Normal Kernel</td>
                <td align="center">Figure 4. Phase Offset of SMI-Enabled Kernel</td>
            </tr>
        </table>
        <h4 id="#phase">Phase and Frequency Offset Characteristics</h4>
        <p>The figures below show the phase and frequency characteristic for the nanosecond kernel (case (2) Figures 5 and 6) and microsecond kernel (case (1) Figures 7 and 8). It is important to remember that the data on these plots are derived from the oscillator control signal <i>V<sub>c</sub></i> of the feedback loop. See the <a href="descrip.htm">Principles of Operation</a> page for further information. For these figures the cesium oscillator and PPS interface were used as the source for the PPS discipline. The cause of the higher wander with case (2) is readily apparent in the frequency offset characteristic of Figure 6, which is considerably more wiggly than Figure 8. In fact, there are some nasty discontinuities in Figure 6 due to extreme temperature variations during the particular experiment run. From experience, Figure 8 is more typical of workstations in temperature controlled office environments. Note also the grass in Figure 8, which is absent in Figure 6. While this does not seriously affect the phase offset, the cause is probably due the fact the microsecond kernel can resolve time values to only 1 <font face="symbol">m</font>s.</p>
        <table width="100%" cols="1">
            <tr>
                <td align="center"><img src="pic/DM41_tp.gif" alt="gif"></td>
                <td align="center"><img src="pic/DM41_fp.gif" alt="gif"></td>
            </tr>
            <tr>
                <td align="center">Figure 5. Phase Offset for Nanosecond Kernel</td>
                <td align="center">Figure 6. Frequency Offset for Nanosecond Kernel</td>
            </tr>
        </table>
        <table width="100%" cols="1">
            <tr>
                <td align="center"><img src="pic/pps1_tp.gif" alt="gif"></td>
                <td align="center"><img src="pic/pps1_fp.gif" alt="gif"></td>
            </tr>
            <tr>
                <td align="center">Figure 7. Phase Offset for Microsecond Kernel</td>
                <td align="center">Figure 8. Frequency Offset for Microsecond Kernel</td>
            </tr>
        </table>
        <p>Figures 9 and 10 show the phase and frequency offsets for the synthetic data of case (4). Here the noise levels are considerably less than the other figures and represent the ultimate performance if the various residual sources of jitter and latency can be found and removed.</p>
        <table width="100%" cols="1">
            <tr>
                <td align="center"><img src="pic/synth1_tp.gif" alt="gif"></td>
                <td align="center"><img src="pic/synth1_fp.gif" alt="gif"></td>
            </tr>
            <tr>
                <td align="center">Figure 9. Phase Offset for Synthetic Kernel</td>
                <td align="center">Figure 10. Frequency Offset for Synthetic Kernel</td>
            </tr>
        </table>
        <h4 id="#avg">The Effects of Averaging Interval</h4>
        <p>Throughout this presentation until this point, it has been assumed that the optimum performance (lowest standard error) is achieved when the averaging interval is equal to the Allan intercept. Figures 11 and 12 show the standard error for the nanosecond kernel (case 2) and microsecond kernel (case 1) as the averaging interval is varied from 4 s to 32768 s.</p>
        <table width="100%" cols="1">
            <tr>
                <td align="center"><img src="pic/DM4_p.gif" alt="gif"></td>
                <td align="center"><img src="pic/pps_p.gif" alt="gif"></td>
            </tr>
            <tr>
                <td align="center">Figure 11. Standard Error for Nanosecond Kernel</td>
                <td align="center">Figure 12. Standard Error for Microsecond Kernel</td>
            </tr>
        </table>
        <p>The lowest standard error is reached at 50 s in Figure 11 and 500 s in Figure 12. These values should be compared with the Allan intercept for each case, 50 s and 2000 s, respectively. While the Allan intercept is an accurate predictor of optimum averaging interval for the nanosecond kernel, it is less so for the microsecond kernel. On the other hand, the valley is quite broad and results in only minor increase in standard error over the range from 100 s to 5000 s. From these data a value of 128 s appears a good compromise choice.</p>
        <p>It should be noted that the PPS discipline uses the averaging interval differently for phase averaging and frequency averaging. An exponential average is used for phase discipline, while a simple average is used for frequency discipline. The weight factor used for the exponential average is the reciprocal of the averaging interval. With this design the combined effect of the two discipline loops becomes marginally stable at the lowest averaging interval of 4 s and explains why the traces shown in the figures rise so fast at the lowest end. The interval of 4 s is used only at startup and after a drastic change in system clock frequency is sensed. The discipline increases the interval after that until reaching the maintaining the interval shown on the plot.</p>
        <h4 id="#ref">References</h4>
        <ol>
            <li>Mills, D.L. Adaptive hybrid clock discipline algorithm for the Network Time Protocol. <i>IEEE/ACM Trans. Networking 6, 5</i> (October 1998), 505-514. <a href="http://www.eecis.udel.edu/~mills/database/papers/allan.ps">PostScript</a> | <a href="http://www.eecis.udel.edu/~mills/database/papers/allan.pdf">PDF</a>
        </ol>
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