/*
//###########################################################################
//
// FILE:    GPRS_Ram.cmd
//
// TITLE:   
//          
// 
// 文件路徑:
//

*/
/* ======================================================
// For Code Composer Studio prior to V2.2
// --------------------------------------
// 1) Use one of the following -l statements to include the 
// header linker command file in the project. The header linker
// file is required to link the peripheral structures to the proper 
// locations within the memory map                                    */

/* Uncomment this line to include file only for non-BIOS applications */
/* -l DSP281x_Headers_nonBIOS.cmd */

/* Uncomment this line to include file only for BIOS applications */
/* -l DSP281x_Headers_BIOS.cmd */

/* 2) In your project add the path to <base>\DSP281x_headers\cmd to the
   library search path under project->build options, linker tab, 
   library search path (-i).
/*========================================================= */

/*		
		PAGE 0 will be used to organize program sections
   		PAGE 1 will be used to organize data sections
*/
MEMORY
{
PAGE 0 :  /* Program Memory */
   		  /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE1 for data allocation */
   /* For this example, H0 is split between PAGE 0 and PAGE 1 */  
   /* BEGIN is used for the "boot to HO" bootloader mode      */
   /* RESET is loaded with the reset vector only if           */
   /* the boot is from XINTF Zone 7.  Otherwise reset vector  */
   /* is fetched from boot ROM. See .reset section below      */
   
   RAMM0       : origin = 0x000000, length = 0x000100
   ZONE0       : origin = 0x002000, length = 0x002000     /* XINTF zone 0 */
   ZONE1       : origin = 0x004000, length = 0x002000     /* XINTF zone 1 */
   RAML0       : origin = 0x008000, length = 0x001000     /* on-chip RAM block L0 */
   ZONE2       : origin = 0x080000, length = 0x080000     /* XINTF zone 2 */
/* ZONE6       : origin = 0x100000, length = 0x080000     /* XINTF zone 6 */
   OTP         : origin = 0x3D7800, length = 0x000800     /* on-chip OTP */
/*   FLASHJ      : origin = 0x3D8000, length = 0x002000     /* on-chip FLASH */
/*   FLASHI      : origin = 0x3DA000, length = 0x002000     /* on-chip FLASH */
/*   FLASHH      : origin = 0x3DC000, length = 0x004000     /* on-chip FLASH */
/*   FLASHG      : origin = 0x3E0000, length = 0x004000     /* on-chip FLASH */
/*   FLASHF      : origin = 0x3E4000, length = 0x004000     /* on-chip FLASH */
/*   FLASHE      : origin = 0x3E8000, length = 0x004000     /* on-chip FLASH */
/*   FLASHD      : origin = 0x3EC000, length = 0x004000     /* on-chip FLASH */
/*   FLASHC      : origin = 0x3F0000, length = 0x004000     /* on-chip FLASH */
/*   FLASHB      : origin = 0x3F4000, length = 0x002000     /* on-chip FLASH */         
/*   FLASHA      : origin = 0x3F6000, length = 0x001F80     /* on-chip FLASH */
   CSM_RSVD    : origin = 0x3F7F80, length = 0x000076     /* Part of FLASHA.  Program with all 0x0000 when CSM is in use. */
   BEGIN       : origin = 0x100000, length = 0x000002     /* Part of FLASHA.  Used for "boot to Flash" bootloader mode. */
/*   BEGIN      : origin = 0x3F7FF6, length = 0x000002  */           
   CSM_PWL     : origin = 0x3F7FF8, length = 0x000008     /* Part of FLASHA.  CSM password locations in FLASHA */
   
   Onchip_Flash : origin = 0x3D8000, length = 0x01FF80
/*   BEGIN      : origin = 0x3F8000, length = 0x000002  */           
   PRAMH0     : origin = 0x3F8002, length = 0x001FFE
   
/* ZONE7       : origin = 0x3FC000, length = 0x003FC0     /* XINTF zone 7 available if MP/MCn=1 */ 
   ROM         : origin = 0x3FF000, length = 0x000FC0     /* Boot ROM available if MP/MCn=0 */
   RESET       : origin = 0x3FFFC0, length = 0x000002     /* part of boot ROM (MP/MCn=0) or XINTF zone 7 (MP/MCn=1) */
   VECTORS     : origin = 0x3FFFC2, length = 0x00003E     /* part of boot ROM (MP/MCn=0) or XINTF zone 7 (MP/MCn=1) */
   SRAM_A      : origin = 0x100002, length = 0x01FFFE     /* 4016V10 ,128K*16bits SRAM */      



PAGE 1 : /* Data Memory */
         /* Memory (RAM/FLASH/OTP) blocks can be moved to PAGE0 for program allocation */
                              /* Registers remain on PAGE1                                                  */


   /* For this example, H0 is split between PAGE 0 and PAGE 1 */

   RAMM1    : origin = 0x000100, length = 0x000700
/*   DRAMH0   : origin = 0x3f9000, length = 0x001000 */
   RAML1    : origin = 0x009000, length = 0x001000     /* on-chip RAM block L1 */
   SRAM_A   : origin = 0x120000, length = 0x020000     /* 4016V10 ,128K*16bits SRAM */
   SRAM_B   : origin = 0x140000, length = 0x040000     /* 4016V10 ,256K*16bits SRAM */
}
 
 
SECTIONS
{
   /* Setup for "boot to H0" mode: 
      The codestart section (found in DSP28_CodeStartBranch.asm)
      re-directs execution to the start of user code.  
      Place this section at the start of H0  */

   codestart        : > BEGIN,       PAGE = 0
   ramfuncs         : LOAD = SRAM_A,PAGE = 0 
                      RUN = RAML0, PAGE = 0
                      RUN_START(_ramfuncs_runstart),
                      LOAD_START(_ramfuncs_loadstart),
                      LOAD_END(_ramfuncs_loadend)
/*	.text            : > SRAM_A,      PAGE = 0  */    /*point to IS62LV1024LL*/
   .text            : > SRAM_A       PAGE = 0
   .cinit           : > SRAM_A       PAGE = 0
   .pinit           : > SRAM_A       PAGE = 0

   .reset           : > RESET,       PAGE = 0, TYPE = DSECT /* not used, */

   /* Allocate uninitalized data sections: */   
   .stack           : > RAMM1,       PAGE = 1
   .ebss            : > SRAM_A,      PAGE = 1   
   .esysmem         : > SRAM_A,      PAGE = 1


   .econst          : > SRAM_A,      PAGE = 1   
   .switch          : > SRAM_A,       PAGE = 0
     RECORDER_SEG   : > SRAM_A,		 PAGE = 1
}



/******************* end of file ************************/