#define CAP2FIFO           *((volatile int *)0x7424)    /*   Capture Channel 2 FIFO Top          */
#define CAP3FIFO           *((volatile int *)0x7425)    /*   Capture Channel 3 FIFO Top          */
#define CAP1FBOT           *((volatile int *)0x7427)    /*   Bottom reg. pf capture FIFO stack 1 */
#define CAP2FBOT           *((volatile int *)0x7427)    /*   Bottom reg. pf capture FIFO stack 2 */
#define CAP3FBOT           *((volatile int *)0x7427)    /*   Bottom reg. pf capture FIFO stack 3 */
#define EVAIMRA            *((volatile int *)0x742C)    /*   Group A Interrupt Mask Register A   */
#define EVAIMRB            *((volatile int *)0x742D)    /*   Group B Interrupt Mask Register A   */
#define EVAIMRC            *((volatile int *)0x742E)    /*   Group C Interrupt Mask Register A   */
#define EVAIFRA            *((volatile int *)0x742F)    /*   Group A Interrupt Flag Register A   */
#define EVAIFRB            *((volatile int *)0x7430)    /*   Group B Interrupt Flag Register A   */
#define EVAIFRC            *((volatile int *)0x7431)    /*   Group C Interrupt Flag Register A   */
#define GPTCONB            *((volatile int *)0x7500)    /*   GP Timer control register B .       */
#define T3CNT              *((volatile int *)0x7501)    /*   GP Timer 3 counter register.        */
#define T3CMPR             *((volatile int *)0x7502)    /*   GP Timer 3 compare register.        */
#define T3PR               *((volatile int *)0x7503)    /*   GP Timer 3 period register.         */
#define T3PER              *((volatile int *)0x7503)    /*   GP Timer 3 period register.         */
#define T3CON              *((volatile int *)0x7504)    /*   GP Timer 3 control register.        */
#define T4CNT              *((volatile int *)0x7505)    /*   GP Timer 4 counter register.        */
#define T4CMPR             *((volatile int *)0x7506)    /*   GP Timer 4 compare register.        */
#define T4PR               *((volatile int *)0x7507)    /*   GP Timer 4 period register.         */
#define T4PER              *((volatile int *)0x7507)    /*   GP Timer 4 period register.         */
#define T4CON              *((volatile int *)0x7508)    /*   GP Timer 4 control register.        */
#define COMCONB            *((volatile int *)0x7511)    /*   Compare control register B.         */
#define ACTRB              *((volatile int *)0x7513)    /*   Full compare action control register*/
#define DBTCONB            *((volatile int *)0x7515)    /*   Dead-band timer control register B. */
#define CMPR4              *((volatile int *)0x7517)    /*   Full compare unit compare register1 */
#define CMPR5              *((volatile int *)0x7518)    /*   Full compare unit compare register2 */
#define CMPR6              *((volatile int *)0x7519)    /*   Full compare unit compare register3 */
#define CAPCONB            *((volatile int *)0x7520)    /*   Capture control register B.         */
#define CAPFIFOB           *((volatile int *)0x7522)    /*   Capture FIFO status register B.     */
#define CAP4FIFO           *((volatile int *)0x7523)    /*   Capture Channel 1 FIFO Top B        */
#define CAP5FIFO           *((volatile int *)0x7524)    /*   Capture Channel 2 FIFO Top B        */
#define CAP6FIFO           *((volatile int *)0x7525)    /*   Capture Channel 3 FIFO Top B        */
#define CAP4FBOT           *((volatile int *)0x7527)    /*   Bottom reg. pf capture FIFO stack 1 */
#define CAP5FBOT           *((volatile int *)0x7527)    /*   Bottom reg. pf capture FIFO stack 2 */
#define CAP6FBOT           *((volatile int *)0x7527)    /*   Bottom reg. pf capture FIFO stack 3 */
#define EVBIMRA            *((volatile int *)0x752C)    /*   Group A Interrupt Mask Register B   */
#define EVBIMRB            *((volatile int *)0x752D)    /*   Group B Interrupt Mask Register B   */
#define EVBIMRC            *((volatile int *)0x752E)    /*   Group C Interrupt Mask Register B   */
#define EVBIFRA            *((volatile int *)0x752F)    /*   Group A Interrupt Flag Register B   */
#define EVBIFRB            *((volatile int *)0x7530)    /*   Group B Interrupt Flag Register B   */
#define EVBIFRC            *((volatile int *)0x7531)    /*   Group C Interrupt Flag Register B   */
#define CANMDER            *((volatile int *)0x7100)    /*   CAN Mailbox Direction/Enable reg    */
#define CANTCR             *((volatile int *)0x7101)    /*   CAN Transmission Control Reg        */
#define CANRCR             *((volatile int *)0x7102)    /*   CAN Recieve COntrol Reg             */
#define CANMCR             *((volatile int *)0x7103)    /*   CAN Master Control Reg              */
#define CANBCR2            *((volatile int *)0x7104)    /*   CAN Bit COnfig Reg 2                */
#define CANBCR1            *((volatile int *)0x7105)    /*   CAN Bit Config Reg 1                */
#define CANESR             *((volatile int *)0x7106)    /*   CAN Error Status Reg                */
#define CANGSR             *((volatile int *)0x7107)    /*   CAN Global Status Reg               */
#define CANCEC             *((volatile int *)0x7108)    /*   CAN Trans and Rcv Err counters      */
#define CANIFR             *((volatile int *)0x7109)    /*   CAN Interrupt Flag Registers        */
#define CANIMR             *((volatile int *)0x710a)    /*   CAN Interrupt Mask Registers        */
#define CANLAM0H           *((volatile int *)0x710b)    /*   CAN Local Acceptance Mask MBx0/1    */
#define CANLAM0L           *((volatile int *)0x710c)    /*   CAN Local Acceptance Mask MBx0/1    */
#define CANLAM1H           *((volatile int *)0x710d)    /*   CAN Local Acceptance Mask MBx2/3    */
#define CANLAM1L           *((volatile int *)0x710e)    /*   CAN Local Acceptance Mask MBx2/3    */
#define CANMSGID0L         *((volatile int *)0x7200)    /*   CAN Message ID for mailbox 0 (lower */
#define CANMSGID0H         *((volatile int *)0x7201)    /*   CAN Message ID for mailbox 0 (upper */
#define CANMSGCTRL0        *((volatile int *)0x7202)    /*   CAN RTR and DLC                     */
#define CANMBX0A           *((volatile int *)0x7204)    /*   CAN 2 of 8 bytes of Mailbox 0       */
#define CANMBX0B           *((volatile int *)0x7205)    /*   CAN 2 of 8 bytes of Mailbox 0       */
#define CANMBX0C           *((volatile int *)0x7206)    /*   CAN 2 of 8 bytes of Mailbox 0       */
#define CANMBX0D           *((volatile int *)0x7207)    /*   CAN 2 of 8 bytes of Mailbox 0       */
#define CANMSGID1L         *((volatile int *)0x7208)    /*   CAN Message ID for mailbox 1 (lower */
#define CANMSGID1H         *((volatile int *)0x7209)    /*   CAN Message ID for mailbox 1 (upper */
#define CANMSGCTRL1        *((volatile int *)0x720A)    /*   CAN RTR and DLC                     */
#define CANMBX1A           *((volatile int *)0x720C)    /*   CAN 2 of 8 bytes of Mailbox 1       */
#define CANMBX1B           *((volatile int *)0x720D)    /*   CAN 2 of 8 bytes of Mailbox 1       */
#define CANMBX1C           *((volatile int *)0x720E)    /*   CAN 2 of 8 bytes of Mailbox 1       */
#define CANMBX1D           *((volatile int *)0x720F)    /*   CAN 2 of 8 bytes of Mailbox 1       */
#define CANMSGID2L         *((volatile int *)0x7210)    /*   CAN Message ID for mailbox 2 (lower */
#define CANMSGID2H         *((volatile int *)0x7211)    /*   CAN Message ID for mailbox 2 (upper */
#define CANMSGCTRL2        *((volatile int *)0x7212)    /*   CAN RTR and DLC                     */
#define CANMBX2A           *((volatile int *)0x7214)    /*   CAN 2 of 8 bytes of Mailbox 2       */
#define CANMBX2B           *((volatile int *)0x7215)    /*   CAN 2 of 8 bytes of Mailbox 2       */
#define CANMBX2C           *((volatile int *)0x7216)    /*   CAN 2 of 8 bytes of Mailbox 2       */
#define CANMBX2D           *((volatile int *)0x7217)    /*   CAN 2 of 8 bytes of Mailbox 2       */
#define CANMSGID3L         *((volatile int *)0x7218)    /*   CAN Message ID for mailbox 3 (lower */
#define CANMSGID3H         *((volatile int *)0x7219)    /*   CAN Message ID for mailbox 3 (upper */
#define CANMSGCTRL3        *((volatile int *)0x721A)    /*   CAN RTR and DLC                     */
#define CANMBX3A           *((volatile int *)0x721C)    /*   CAN 2 of 8 bytes of Mailbox 3       */
#define CANMBX3B           *((volatile int *)0x721D)    /*   CAN 2 of 8 bytes of Mailbox 3       */
#define CANMBX3C           *((volatile int *)0x721E)    /*   CAN 2 of 8 bytes of Mailbox 3       */
#define CANMBX3D           *((volatile int *)0x721F)    /*   CAN 2 of 8 bytes of Mailbox 3       */
#define CANMSGID4L         *((volatile int *)0x7220)    /*   CAN Message ID for mailbox 4 (lower */
#define CANMSGID4H         *((volatile int *)0x7221)    /*   CAN Message ID for mailbox 4 (upper */
#define CANMSGCTRL4        *((volatile int *)0x7222)    /*   CAN RTR and DLC                     */
#define CANMBX4A           *((volatile int *)0x7224)    /*   CAN 2 of 8 bytes of Mailbox 4       */
#define CANMBX4B           *((volatile int *)0x7225)    /*   CAN 2 of 8 bytes of Mailbox 4       */
#define CANMBX4C           *((volatile int *)0x7226)    /*   CAN 2 of 8 bytes of Mailbox 4       */
#define CANMBX4D           *((volatile int *)0x7227)    /*   CAN 2 of 8 bytes of Mailbox 4       */
#define CANMSGID5L         *((volatile int *)0x7228)    /*   CAN Message ID for mailbox 5 (lower */
#define CANMSGID5H         *((volatile int *)0x7229)    /*   CAN Message ID for mailbox 5 (upper */
#define CANMSGCTRL5        *((volatile int *)0x722A)    /*   CAN RTR and DLC                     */
#define CANMBX5A           *((volatile int *)0x722C)    /*   CAN 2 of 8 bytes of Mailbox 5       */
#define CANMBX5B           *((volatile int *)0x722D)    /*   CAN 2 of 8 bytes of Mailbox 5       */
#define CANMBX5C           *((volatile int *)0x722E)    /*   CAN 2 of 8 bytes of Mailbox 5       */
#define CANMBX5D           *((volatile int *)0x722F)    /*   CAN 2 of 8 bytes of Mailbox 5       */
/*--------------------------------------------------------------------------*/
/* I/O space mapped registers                           */
/*--------------------------------------------------------------------------*/
#define WSGR    portffff    
ioport unsigned portffff;       /* Wait-State Generator Control Reg */

#define FCMR    portff0f    /* Flash mode control register */
ioport unsigned portff0f;

#endif /*__REGS240X_H__  */