#define SHIFT5(x)	((x) << 5)#define SHIFT4(x)	((x) << 4)#define SHIFT3(x)	((x) << 3)#define SHIFT2(x)	((x) << 2)#define SHIFT1(x)	((x) << 1)#define SHIFT0(x)	((x) << 0)/* * Configuration Space header * Since this module is used for different OS', those may be * duplicate on some of them (e.g. Linux). But to keep the * common source, we have to live with this... */#define PCI_VENDOR_ID	0x00	/* 16 bit	Vendor ID */#define PCI_DEVICE_ID	0x02	/* 16 bit	Device ID */#define PCI_COMMAND		0x04	/* 16 bit	Command */#define PCI_STATUS		0x06	/* 16 bit	Status */#define PCI_REV_ID		0x08	/*  8 bit	Revision ID */#if 0#define PCI_CLASS_CODE	0x09	/* 24 bit	Class Code */#endif#define PCI_CACHE_LSZ	0x0c	/*  8 bit	Cache Line Size */#define PCI_LAT_TIM		0x0d	/*  8 bit	Latency Timer */#define PCI_HEADER_T	0x0e	/*  8 bit	Header Type */#define PCI_BIST		0x0f	/*  8 bit	Built-in selftest */#define PCI_BASE_1ST	0x10	/* 32 bit	1st Base address */#define PCI_BASE_2ND	0x14	/* 32 bit	2nd Base address */	/* Byte 0x18..0x2b:	reserved */#define PCI_SUB_VID		0x2c	/* 16 bit	Subsystem Vendor ID */#define PCI_SUB_ID		0x2e	/* 16 bit	Subsystem ID */#define PCI_BASE_ROM	0x30	/* 32 bit	Expansion ROM Base Address */#define PCI_CAP_PTR		0x34	/*  8 bit 	Capabilities Ptr */	/* Byte 35..3b:	reserved */#define PCI_IRQ_LINE	0x3c	/*  8 bit	Interrupt Line */#define PCI_IRQ_PIN		0x3d	/*  8 bit	Interrupt Pin */#define PCI_MIN_GNT		0x3e	/*  8 bit	Min_Gnt */#define PCI_MAX_LAT		0x3f	/*  8 bit	Max_Lat */	/* Device Dependent Region */#define PCI_OUR_REG_1	0x40	/* 32 bit 	Our Register 1 */#define PCI_OUR_REG_2	0x44	/* 32 bit 	Our Register 2 */	/* Power Management Region */#define PCI_PM_CAP_ID	0x48	/*  8 bit 	Power Management Cap. ID */#define PCI_PM_NITEM	0x49	/*  8 bit 	Next Item Ptr */#define PCI_PM_CAP_REG	0x4a	/* 16 bit 	Power Management Capabilities */#define PCI_PM_CTL_STS	0x4c	/* 16 bit 	Power Manag. Control/Status */	/* Byte 0x4e:	reserved */#define PCI_PM_DAT_REG	0x4f	/*  8 bit 	Power Manag. Data Register */	/* VPD Region */#define PCI_VPD_CAP_ID	0x50	/*  8 bit 	VPD Cap. ID */#define PCI_VPD_NITEM	0x51	/*  8 bit 	Next Item Ptr */#define PCI_VPD_ADR_REG	0x52	/* 16 bit 	VPD Address Register */#define PCI_VPD_DAT_REG	0x54	/* 32 bit 	VPD Data Register */	/* Byte 0x58..0xff:	reserved *//* * I2C Address (PCI Config) * * Note: The temperature and voltage sensors are relocated on a different *	 I2C bus. */#define I2C_ADDR_VPD	0xA0	/* I2C address for the VPD EEPROM *//* * Define Bits and Values of the registers *//*	PCI_COMMAND	16 bit	Command */								/* Bit 15..11:	reserved */#define PCI_INT_DIS		BIT_10S		/* Interrupt INTx# disable (PCI 2.3) */#define PCI_FBTEN		BIT_9S		/* Fast Back-To-Back enable */#define PCI_SERREN		BIT_8S		/* SERR enable */#define PCI_ADSTEP		BIT_7S		/* Address Stepping */#define PCI_PERREN		BIT_6S		/* Parity Report Response enable */#define PCI_VGA_SNOOP	BIT_5S		/* VGA palette snoop */#define PCI_MWIEN		BIT_4S		/* Memory write an inv cycl ena */#define PCI_SCYCEN		BIT_3S		/* Special Cycle enable */#define PCI_BMEN		BIT_2S		/* Bus Master enable */#define PCI_MEMEN		BIT_1S		/* Memory Space Access enable */#define PCI_IOEN		BIT_0S		/* I/O Space Access enable */#define PCI_COMMAND_VAL	(PCI_FBTEN | PCI_SERREN | PCI_PERREN | PCI_MWIEN |\						 PCI_BMEN | PCI_MEMEN | PCI_IOEN)/*	PCI_STATUS	16 bit	Status */#define PCI_PERR		BIT_15S		/* Parity Error */#define PCI_SERR		BIT_14S		/* Signaled SERR */#define PCI_RMABORT		BIT_13S		/* Received Master Abort */#define PCI_RTABORT		BIT_12S		/* Received Target Abort */								/* Bit 11:	reserved */#define PCI_DEVSEL		(3<<9)		/* Bit 10.. 9:	DEVSEL Timing */#define PCI_DEV_FAST	(0<<9)		/*		fast */#define PCI_DEV_MEDIUM	(1<<9)		/*		medium */#define PCI_DEV_SLOW	(2<<9)		/*		slow */#define PCI_DATAPERR	BIT_8S		/* DATA Parity error detected */#define PCI_FB2BCAP		BIT_7S		/* Fast Back-to-Back Capability */#define PCI_UDF			BIT_6S		/* User Defined Features */#define PCI_66MHZCAP	BIT_5S		/* 66 MHz PCI bus clock capable */#define PCI_NEWCAP		BIT_4S		/* New cap. list implemented */#define PCI_INT_STAT	BIT_3S		/* Interrupt INTx# Status (PCI 2.3) */								/* Bit  2.. 0:	reserved */#define PCI_ERRBITS	(PCI_PERR | PCI_SERR | PCI_RMABORT | PCI_RTABORT |\			PCI_DATAPERR)/*	PCI_CLASS_CODE	24 bit	Class Code *//*	Byte 2:		Base Class		(02) *//*	Byte 1:		SubClass		(00) *//*	Byte 0:		Programming Interface	(00) *//*	PCI_CACHE_LSZ	8 bit	Cache Line Size *//*	Possible values: 0,2,4,8,16,32,64,128	*//*	PCI_HEADER_T	8 bit	Header Type */#define PCI_HD_MF_DEV	BIT_7S	/* 0= single, 1= multi-func dev */#define PCI_HD_TYPE		0x7f	/* Bit 6..0:	Header Layout 0= normal *//*	PCI_BIST	8 bit	Built-in selftest *//*	Built-in Self test not supported (optional) *//*	PCI_BASE_1ST	32 bit	1st Base address */#define PCI_MEMSIZE		0x4000L		/* use 16 kB Memory Base */#define PCI_MEMBASE_MSK 0xffffc000L	/* Bit 31..14:	Memory Base Address */#define PCI_MEMSIZE_MSK 0x00003ff0L	/* Bit 13.. 4:	Memory Size Req. */#define PCI_PREFEN		BIT_3		/* Prefetchable */#define PCI_MEM_TYP		(3L<<2)		/* Bit	2.. 1:	Memory Type */#define PCI_MEM32BIT	(0L<<1)		/* Base addr anywhere in 32 Bit range */#define PCI_MEM1M		(1L<<1)		/* Base addr below 1 MegaByte */#define PCI_MEM64BIT	(2L<<1)		/* Base addr anywhere in 64 Bit range */#define PCI_MEMSPACE	BIT_0		/* Memory Space Indic. *//*	PCI_BASE_2ND	32 bit	2nd Base address */#define PCI_IOBASE		0xffffff00L	/* Bit 31.. 8:	I/O Base address */#define PCI_IOSIZE		0x000000fcL	/* Bit	7.. 2:	I/O Size Requirements */									/* Bit	1:	reserved */#define PCI_IOSPACE		BIT_0		/* I/O Space Indicator *//*	PCI_BASE_ROM	32 bit	Expansion ROM Base Address */#define PCI_ROMBASE		0xfffe0000L	/* Bit 31..17:	ROM BASE address (1st)*/#define PCI_ROMBASZ		(0x1cL<<14)	/* Bit 16..14:	Treat as BASE or SIZE */#define PCI_ROMSIZE		(0x38L<<11)	/* Bit 13..11:	ROM Size Requirements */									/* Bit 10.. 1:	reserved */#define PCI_ROMEN		BIT_0		/* Address Decode enable *//* Device Dependent Region *//*	PCI_OUR_REG_1		32 bit	Our Register 1 */									/* Bit 31..29:	reserved */#define PCI_PHY_COMA	BIT_28		/* Set PHY to Coma Mode */#define PCI_EN_CAL		BIT_27		/* Enable  PCI buffer strength calibr. */#define PCI_DIS_CAL		BIT_26		/* Disable PCI buffer strength calibr. */#define PCI_VIO			BIT_25		/* PCI I/O Voltage, 0 = 3.3V, 1 = 5V */#define PCI_DIS_BOOT	BIT_24		/* Disable BOOT via ROM */#define PCI_EN_IO		BIT_23		/* Mapping to I/O space */#define PCI_EN_FPROM	BIT_22		/* Enable FLASH mapping to memory */									/*		1 = Map Flash to memory */									/*		0 = Disable addr. dec */#define PCI_PAGESIZE	(3L<<20)	/* Bit 21..20:	FLASH Page Size	*/#define PCI_PAGE_16		(0L<<20)	/*		16 k pages	*/#define PCI_PAGE_32K	(1L<<20)	/*		32 k pages	*/#define PCI_PAGE_64K	(2L<<20)	/*		64 k pages	*/#define PCI_PAGE_128K	(3L<<20)	/*		128 k pages	*/									/* Bit 19:	reserved	*/#define PCI_PAGEREG		(7L<<16)	/* Bit 18..16:	Page Register	*/#define PCI_NOTAR		BIT_15		/* No turnaround cycle */#define PCI_FORCE_BE	BIT_14		/* Assert all BEs on MR */#define PCI_DIS_MRL		BIT_13		/* Disable Mem Read Line */#define PCI_DIS_MRM		BIT_12		/* Disable Mem Read Multiple */#define PCI_DIS_MWI		BIT_11		/* Disable Mem Write & Invalidate */#define PCI_DISC_CLS	BIT_10		/* Disc: cacheLsz bound */#define PCI_BURST_DIS	BIT_9		/* Burst Disable */#define PCI_DIS_PCI_CLK	BIT_8		/* Disable PCI clock driving */#define PCI_SKEW_DAS	(0xfL<<4)	/* Bit	7.. 4:	Skew Ctrl, DAS Ext */#define PCI_SKEW_BASE	0xfL		/* Bit	3.. 0:	Skew Ctrl, Base	*//*	PCI_OUR_REG_2		32 bit	Our Register 2 */#define PCI_VPD_WR_THR	(0xffL<<24)	/* Bit 31..24:	VPD Write Threshold */#define PCI_DEV_SEL		(0x7fL<<17)	/* Bit 23..17:	EEPROM Device Select */#define PCI_VPD_ROM_SZ	(7L<<14)	/* Bit 16..14:	VPD ROM Size	*/									/* Bit 13..12:	reserved	*/#define PCI_PATCH_DIR	(0xfL<<8)	/* Bit 11.. 8:	Ext Patches dir 3..0 */#define PCI_PATCH_DIR_3	BIT_11#define PCI_PATCH_DIR_2	BIT_10#define PCI_PATCH_DIR_1	BIT_9#define PCI_PATCH_DIR_0	BIT_8#define PCI_EXT_PATCHS	(0xfL<<4)	/* Bit	7.. 4:	Extended Patches 3..0 */#define PCI_EXT_PATCH_3	BIT_7#define PCI_EXT_PATCH_2	BIT_6#define PCI_EXT_PATCH_1	BIT_5#define PCI_EXT_PATCH_0	BIT_4#define PCI_EN_DUMMY_RD	BIT_3		/* Enable Dummy Read */#define PCI_REV_DESC	BIT_2		/* Reverse Desc. Bytes */									/* Bit	1:	reserved */#define PCI_USEDATA64	BIT_0		/* Use 64Bit Data bus ext *//* Power Management Region *//*	PCI_PM_CAP_REG		16 bit	Power Management Capabilities */#define PCI_PME_SUP_MSK	(0x1f<<11)	/* Bit 15..11:	PM Event Support Mask */#define PCI_PME_D3C_SUP	BIT_15S		/* PME from D3cold Support (if Vaux) */#define PCI_PME_D3H_SUP	BIT_14S		/* PME from D3hot Support */#define PCI_PME_D2_SUP	BIT_13S		/* PME from D2 Support */#define PCI_PME_D1_SUP	BIT_12S		/* PME from D1 Support */#define PCI_PME_D0_SUP	BIT_11S		/* PME from D0 Support */#define PCI_PM_D2_SUP	BIT_10S		/* D2 Support in 33 MHz mode */#define PCI_PM_D1_SUP	BIT_9S		/* D1 Support */									/* Bit	8.. 6:	reserved */#define PCI_PM_DSI		BIT_5S		/* Device Specific Initialization */#define PCI_PM_APS		BIT_4S		/* Auxialiary Power Source */#define PCI_PME_CLOCK	BIT_3S		/* PM Event Clock */#define PCI_PM_VER_MSK		7		/* Bit	2.. 0:	PM PCI Spec. version *//*	PCI_PM_CTL_STS		16 bit	Power Management Control/Status */#define PCI_PME_STATUS	BIT_15S		/* PME Status (YUKON only) */#define PCI_PM_DAT_SCL	(3<<13)		/* Bit 14..13:	Data Reg. scaling factor */#define PCI_PM_DAT_SEL	(0xf<<9)	/* Bit 12.. 9:	PM data selector field */#define PCI_PME_EN		BIT_8S		/* Enable PME# generation (YUKON only) */									/* Bit	7.. 2:	reserved */#define PCI_PM_STATE_MSK	3		/* Bit	1.. 0:	Power Management State */#define PCI_PM_STATE_D0		0		/* D0:	Operational (default) */#define PCI_PM_STATE_D1		1		/* D1:	(YUKON only) */#define PCI_PM_STATE_D2		2		/* D2:	(YUKON only) */#define PCI_PM_STATE_D3 	3		/* D3:	HOT, Power Down and Reset *//* VPD Region *//*	PCI_VPD_ADR_REG		16 bit	VPD Address Register */#define PCI_VPD_FLAG	BIT_15S		/* starts VPD rd/wr cycle */#define PCI_VPD_ADR_MSK	0x7fffL		/* Bit 14.. 0:	VPD address mask *//*	Control Register File (Address Map) *//* *	Bank 0 */#define B0_RAP			0x0000	/*  8 bit	Register Address Port */	/* 0x0001 - 0x0003:	reserved */#define B0_CTST			0x0004	/* 16 bit	Control/Status register */#define B0_LED			0x0006	/*  8 Bit	LED register */#define B0_POWER_CTRL	0x0007	/*  8 Bit	Power Control reg (YUKON only) */#define B0_ISRC			0x0008	/* 32 bit	Interrupt Source Register */#define B0_IMSK			0x000c	/* 32 bit	Interrupt Mask Register */#define B0_HWE_ISRC		0x0010	/* 32 bit	HW Error Interrupt Src Reg */#define B0_HWE_IMSK		0x0014	/* 32 bit	HW Error Interrupt Mask Reg */#define B0_SP_ISRC		0x0018	/* 32 bit	Special Interrupt Source Reg */	/* 0x001c:		reserved *//* B0 XMAC 1 registers (GENESIS only) */#define B0_XM1_IMSK		0x0020	/* 16 bit r/w	XMAC 1 Interrupt Mask Register*/	/* 0x0022 - 0x0027:	reserved */#define B0_XM1_ISRC		0x0028	/* 16 bit ro	XMAC 1 Interrupt Status Reg */	/* 0x002a - 0x002f:	reserved */#define B0_XM1_PHY_ADDR 0x0030	/* 16 bit r/w	XMAC 1 PHY Address Register */	/* 0x0032 - 0x0033:	reserved */#define B0_XM1_PHY_DATA 0x0034	/* 16 bit r/w	XMAC 1 PHY Data Register */	/* 0x0036 - 0x003f:	reserved *//* B0 XMAC 2 registers (GENESIS only) */#define B0_XM2_IMSK		0x0040	/* 16 bit r/w	XMAC 2 Interrupt Mask Register*/	/* 0x0042 - 0x0047:	reserved */#define B0_XM2_ISRC		0x0048	/* 16 bit ro	XMAC 2 Interrupt Status Reg */	/* 0x004a - 0x004f:	reserved */#define B0_XM2_PHY_ADDR 0x0050	/* 16 bit r/w	XMAC 2 PHY Address Register */	/* 0x0052 - 0x0053:	reserved */#define B0_XM2_PHY_DATA 0x0054	/* 16 bit r/w	XMAC 2 PHY Data Register */	/* 0x0056 - 0x005f:	reserved *//* BMU Control Status Registers */#define B0_R1_CSR		0x0060	/* 32 bit	BMU Ctrl/Stat Rx Queue 1 */#define B0_R2_CSR		0x0064	/* 32 bit	BMU Ctrl/Stat Rx Queue 2 */#define B0_XS1_CSR		0x0068	/* 32 bit	BMU Ctrl/Stat Sync Tx Queue 1 */#define B0_XA1_CSR		0x006c	/* 32 bit	BMU Ctrl/Stat Async Tx Queue 1*/#define B0_XS2_CSR		0x0070	/* 32 bit	BMU Ctrl/Stat Sync Tx Queue 2 */#define B0_XA2_CSR		0x0074	/* 32 bit	BMU Ctrl/Stat Async Tx Queue 2*/	/* 0x0078 - 0x007f:	reserved *//* *	Bank 1 *	- completely empty (this is the RAP Block window) *	Note: if RAP = 1 this page is reserved *//* *	Bank 2 *//* NA reg = 48 bit Network Address Register, 3x16 or 8x8 bit readable */#define B2_MAC_1		0x0100	/* NA reg	 MAC Address 1 */	/* 0x0106 - 0x0107:	reserved */#define B2_MAC_2		0x0108	/* NA reg	 MAC Address 2 */	/* 0x010e - 0x010f:	reserved */#define B2_MAC_3		0x0110	/* NA reg	 MAC Address 3 */	/* 0x0116 - 0x0117:	reserved */#define B2_CONN_TYP		0x0118	/*  8 bit	Connector type */#define B2_PMD_TYP		0x0119	/*  8 bit	PMD type */#define B2_MAC_CFG		0x011a	/*  8 bit	MAC Configuration / Chip Revision */#define B2_CHIP_ID		0x011b	/*  8 bit 	Chip Identification Number */	/* Eprom registers are currently of no use */#define B2_E_0			0x011c	/*  8 bit	EPROM Byte 0 (ext. SRAM size */#define B2_E_1			0x011d	/*  8 bit	EPROM Byte 1 (PHY type) */#define B2_E_2			0x011e	/*  8 bit	EPROM Byte 2 */#define B2_E_3			0x011f	/*  8 bit	EPROM Byte 3 */#define B2_FAR			0x0120	/* 32 bit	Flash-Prom Addr Reg/Cnt */#define B2_FDP			0x0124	/*  8 bit	Flash-Prom Data Port */	/* 0x0125 - 0x0127:	reserved */#define B2_LD_CRTL		0x0128	/*  8 bit	EPROM loader control register */#define B2_LD_TEST		0x0129	/*  8 bit	EPROM loader test register */	/* 0x012a - 0x012f:	reserved */#define B2_TI_INI		0x0130	/* 32 bit	Timer Init Value */#define B2_TI_VAL		0x0134	/* 32 bit	Timer Value */#define B2_TI_CRTL		0x0138	/*  8 bit	Timer Control */#define B2_TI_TEST		0x0139	/*  8 Bit	Timer Test */	/* 0x013a - 0x013f:	reserved */#define B2_IRQM_INI		0x0140	/* 32 bit	IRQ Moderation Timer Init Reg.*/