/******************************************************************************
**																			 **
**	 Name: 	BF537 EZ-KIT Blink LEDs 										 **
**																			 ** 
*******************************************************************************

(C) Copyright 2004 - Analog Devices, Inc.  All rights reserved.

File Name:		BF537_EZ-KIT_BlinkLeds.asm

Date Modified:	12/10/04		GO		
				
Software:       VisualDSP++4.0

Hardware:		ADSP-BF537 EZ-KIT Board Rev. 1.0
				ADSP-BF537 Rev. 0.0 Silicon

Special Connections:  SW5 on EZ-KIT Board, pins 1-4 should be ON.

Purpose:		Toggle LEDs on the EZ-KIT
				
				
********************************************************************************/

#include <defBF537.h>

//#define SDRAM_START_ADDRESS 	0x4        // switch SW13, LED pattern 0 (PF2)
//#define FLASH_ROM_START_ADDRESS 0x20000000        // switch SW12, LED pattern 1 (PF3)
//#define DATA_ASRAM_START		0xFF800041

.section L1_code;//L1_code_cache;//L1_code;
.global _init_SDRAM;

_init_SDRAM:
	[--SP] = ASTAT;			//Save Regs onto stack
	[--SP] = RETS;
	[--SP] = (r7:0);
	[--SP] = (p5:0);
	[--SP] = I0;
	[--SP] = I1;
	[--SP] = I2;
	[--SP] = I3;
	[--SP] = B0;
	[--SP] = B1;
	[--SP] = B2;
	[--SP] = B3;
	[--SP] = M0;
	[--SP] = M1;
	[--SP] = M2;
	[--SP] = M3;
	[--SP] = L0;
	[--SP] = L1;
	[--SP] = L2;
	[--SP] = L3;

	P0.L = lo(EBIU_SDRRC); 
	P0.H = hi(EBIU_SDRRC); 		//SDRAM Refresh Rate Control Register
	R0 = 0x03A0(Z); 			 					
	W[P0] = R0;							
	SSYNC;	

	P0.L = lo(EBIU_SDBCTL); 			
	P0.H = hi(EBIU_SDBCTL); 	//SDRAM Memory Bank Control Register
	r0 = 0x25(z);   
	[P0] = R0;
	SSYNC;		

	P0.L = lo(EBIU_SDGCTL); 			
	P0.H = hi(EBIU_SDGCTL);		//SDRAM Memory Global Control Register
	R0.L = 0x998D;
	R0.H = 0x0091;
	[P0] = R0;
	SSYNC;

	L3 = [SP++];		//Restore Regs from Stack
	L2 = [SP++];	
	L1 = [SP++];
	L0 = [SP++];
	M3 = [SP++];
	M2 = [SP++];
	M1 = [SP++];
	M0 = [SP++];
	B3 = [SP++];
	B2 = [SP++];
	B1 = [SP++];
	B0 = [SP++];
	I3 = [SP++];
	I2 = [SP++];
	I1 = [SP++];
	I0 = [SP++];
	(p5:0) = [SP++];  		
	(r7:0) = [SP++];
	RETS = [SP++];
	ASTAT = [SP++];
	rts;
	
_init_SDRAM.END: