;GetFLASHType $w4, $w1, $w2, $w3, $w5, $w6, $w7
        ; insert the flash type into the config reg
        orr     $w8,  $w8,  $w4,  LSL  #12

        ; determine bus speed
        ;getHexSwitchLo $w2                     ; read S14 for bus speed, flash page mode, bus width
        ands    $w1,  $w2,  #S14_BUSSPEED      ; test for bus speed
        bicne   $w8,  $w8,  #HwConfig_BusSPEED ; 0=51.5mhz
        orreq   $w8,  $w8,  #HwConfig_BusSPEED ; 1=103mhz

        ; turn page mode off?
        ands    $w1,  $w2,  #S14_PAGEMODE      ; test for "page mode off" switch setting
        bicne   $w8,  $w8,  #HwConfig_PAGEMODE ; clear page mode bits

        ; determine bus width - for all banks
        ands    $w1,  $w2,  #S14_BUSWIDTH      ; test for bus width = 16 bits
        bicne   $w8,  $w8,  #HwConfig_BusWIDTH ; 0=16 bit
        orreq   $w8,  $w8,  #HwConfig_BusWIDTH ; 1=32 bit

        ; determine pll speed
        ;getHexSwitchHi $w2                     ; read S13 for debug port, debug mode, pll
        ands    $w1,  $w2,  #S13_PLLSPEED
        bicne   $w8,  $w8,  #HwConfig_PLL      ; 0=?? mhz
        orreq   $w8,  $w8,  #HwConfig_PLL      ; 1=206mhz

        ; determine debug port
        ands    $w1,  $w2,  #S13_DEBUGPORT
        bicne   $w8,  $w8,  #HwConfig_PORT     ; 0=uart1
        orreq   $w8,  $w8,  #HwConfig_PORT     ; 1=uart3

        ; determine debug mode
        ands    $w1,  $w2,  #S13_DEBUGMODE
        biceq   $w8,  $w8,  #HwConfig_DbgMODE  ; 0=off (default)
        orrne   $w8,  $w8,  #HwConfig_DbgMODE  ; 1=on
;ENDIF
        
PostDetection

        ; get ScratchPad's current value (initHWConfig should already have executed)
        ldr     $w3, =PSPR_BASE_PHYSICAL
        ldr     $w3, [$w3]

        ; orr in the new bits
        orr     $w8,  $w8,  $w3
 
        ; ensure that the sleep reset valid bit is clear - this should only
        ; be set by an app that is prepared to handle a sleep reset.
        bic     $w8,  $w8,  #HwConfig_RESET

        ; write back the new value
        ldr     $w2, =PSPR_BASE_PHYSICAL
        str     $w8, [$w2]

    MEND


; //////////////////////////////////////////////////////////////////////    
        
	MACRO
	mtc15	$cpureg, $cp15reg
	mcr	p15,0,$cpureg,$cp15reg,c0,0
	MEND

	MACRO
	mfc15	$cpureg, $cp15reg
	mrc	p15,0,$cpureg,$cp15reg,c0,0
	MEND
    
    
    
; **** Macro DisableInts *********************************************
; * Params: $gp1 (scratch reg)
; *         
; * Returns: nothing
; *
; *  This macro disables both IRQ and FIQ nondestructively
; ********************************************************************
    MACRO
    DisableInts $gp1
        MRS $gp1, cpsr                                ; Get value of CPSR 
        ORR $gp1, $gp1, #NoIntsMask                ; Set IRQ and FIQ-disabling bits
        MSR cpsr_c, $gp1                                    ; Disable the IRQ/FIQ
    MEND


;
; **** Macro EnableInts *********************************************
; * Params: $gp1 (scratch reg)
; *         
; * Returns: nothing
; *
; *  This macro enables both IRQ and FIQ nondestructively
; ********************************************************************
    MACRO
    EnableInts $gp1
        MRS $gp1, cpsr                     ; Get value of CPSR 
		AND $gp1, $gp1, #IrqFiqEnable      ; Set enable/disable bits
        MSR cpsr_c, $gp1                   ; Control the IRQ/FIQ
    MEND
    

;
; **** Macro InitFFUART *********************************************
; * Params: $FBA (FFUart Base Address )$gp2, $gp3 (scratch regs)
; *         
; * Returns: nothing
; *
; * Registers:  PReserves $FBA, corrupts the rest
; *
; *  This macro inits the FFUART in non-polled, non-FIFO mode at 38400 baud.
; ********************************************************************
    MACRO
    InitFFUART $FBA, $gp2, $gp3


    ;ldr $FBA, =FFUART_BASE_U_VIRTUAL

	; Disable UART and disable interrupts
	ldr $gp2, =0x0
	str $gp2, [$FBA, #0x0c]	; (DLAB OFF)
	str $gp2, [$FBA, #0x04]	; IER_DLH = 0x0

	; Set baud rate divisor (115200 baud)
	ldr $gp2, =0x80		
	str $gp2, [$FBA, #0x0c]	; (DLAB ON)
	ldr $gp2, =0x08		
	str $gp2, [$FBA]		; THR_RBR_DLL = 0x08
	ldr $gp2, =0x0
	str $gp2, [$FBA, #0x04]	; IER_DLH = 0x0

	; Set communications parameters to 8,N,1
	ldr $gp2, =0x0
	str $gp2, [$FBA, #0x0c]	; (DLAB OFF)
	ldr $gp2, =0x3
	str $gp2, [$FBA, #0x0c]	; LCR = 0x3

	; Clear and enable fifos
	ldr $gp2, =0x7
	str $gp2, [$FBA, #0x08]	; IIR_FCR = 0x8

	; Set polled mode
	ldr $gp2, =0x0
	str $gp2, [$FBA, #0x04]	; IER_DLH = 0x0

	; Set normal UART mode
	ldr $gp2, =0x0
	str $gp2, [$FBA, #0x10]	; MCR = 0


    ; Enable UART
	ldr $gp2, [$FBA, #0x04]	; $gp2 = IER_DLH
	orr $gp2, $gp2, #0x40	; Set the enable uart bit
	str $gp2, [$FBA, #0x04]	; 

        
    MEND    


;
; **** Macro PrintStr *********************************************
; * Params: $FBA (FFUART Base Address), $pStr (pointer to string), $gp1
; *         
; * Returns: nothing
; *
; * Effects: Corrupts $pStr & $gp1, preserves $FBA
; *
; *  This macro writes the string pointed to by $pSTr until a '0' is reached.
; ********************************************************************
    MACRO
    PrintStr $FBA, $pStr, $gp1
        

10
        ldrb    $gp1, [$pStr]        ; load the first byte
        cmp     $gp1, #0             ; is it NULL?
        beq     %FT20                 ; if so, let's end now (search forward, this macro only)
        
        IsTBE   $FBA, $gp1           ; ensure TBE
        ldrb    $gp1, [$pStr]        ; load the first byte (agin, for now... really need another register)
        
        strb    $gp1, [$FBA]         ; transmit a byte
        add     $pStr, $pStr, #1     ;  and increment the byte pointer
        b       %BT10                 ; otherwise, keep looping (search backwards, this macro only)
        
20

    MEND


;
; **** Macro IsTBE *********************************************
; * Params: $FBA (FFUART Base Address), $gp1 (scratch reg)
; *         
; * Returns: nothing
; *
; * Effects: Corrupts $gp1, preserves $FBA
; *
; *  This macro spins until FFUART.LSR.TEMT gets set, indicating it
; *    is ready for data.
; ********************************************************************

    MACRO
    IsTBE $FBA, $gp1

10
    ldr  $gp1, [$FBA, #FF_LSR_OFFSET]
    ands $gp1, $gp1, #0x40    ; mask all but bit 6, and set Z if result=0 (i.e. if bit not set)
    beq  %BT10
    
    MEND


;
; **** Macro SCRUB_SDRAM *********************************************
; * Params: $StartAdx: 32-bit aligned start address.
; *         $NumMB   : Number of MB to clear.
; *         $gp1,2   : general purpose scratch
; *         
; * Returns: nothing
; *
; * Effects: corrupts $gp1,2
; *
; *  This macro simply zeros out RAM, ending at $StartAdx, and
; *    starting at ($StartAdx + ($NumMB*0x100000)), inclusive.  It is the resposibility of the
; *    caller to ensure that the addresses are valid!  Ensure $StartAdx
; *    is 32-bit aligned, or my math will get hosed.  I will not alter
; *    the $StartAdx parameter to ensure this alignment!
; *
; Ex:
;    ldr r0, =0xA0000000     ; start Adx
;    mov r1, #64             ; #MB
;
;    SCRUB_SDRAM r0, r1, r2, r3
;
; ********************************************************************

    MACRO
    SCRUB_SDRAM $StartAdx, $NumMB, $gp1, $gp2
    ;
    ; Determine ending address: endAdx = (($NumMB * 0x0010 0000) + $StartAdx)
    ;
    mov     $gp1, #0x100000
    mla     $gp2, $NumMB, $gp1, $StartAdx      

    ldr     $gp1, =0x00000000           ; source data
10    
    sub     $gp2, $gp2, #4              ; word pre-decrement

    str     $gp1, [$gp2]                ; 32-bit zero fill
    cmp     $gp2, $StartAdx
    bne     %BT10                                      
    
    MEND
    
;---------------------------------

    ENDIF
    END