?? fft_system.ptf
字號:
SYSTEM FFT_system
{
System_Wizard_Version = "6.00";
System_Wizard_Build = "168";
WIZARD_SCRIPT_ARGUMENTS
{
device_family = "CYCLONE";
clock_freq = "80000000";
generate_hdl = "1";
generate_sdk = "0";
do_build_sim = "1";
hardcopy_compatible = "0";
board_class = "altera_nios_dev_board_cyclone_2c35";
CLOCKS
{
CLOCK sysclk
{
frequency = "80000000";
source = "External";
Is_Clock_Source = "0";
display_name = "sysclk";
pipeline = "0";
BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
{
pin_assignment = "";
component_pin = "use_quartus_pin_assignment";
}
}
}
hdl_language = "verilog";
device_family_id = "CYCLONEII";
view_master_columns = "1";
view_master_priorities = "0";
name_column_width = "75";
desc_column_width = "75";
bustype_column_width = "0";
base_column_width = "75";
clock_column_width = "80";
end_column_width = "75";
BOARD_INFO
{
CONFIGURATION epcs
{
length = "";
menu_position = "2";
offset = "0x0";
reference_designator = "U69";
}
CONFIGURATION factory
{
length = "";
menu_position = "3";
offset = "0xE00000";
reference_designator = "U5";
}
CONFIGURATION user
{
length = "";
menu_position = "1";
offset = "0xC00000";
reference_designator = "U5";
}
JTAG_device_index = "1";
REFDES U5
{
base = "0x01000000";
}
REFDES U69
{
base = "0x00060000";
}
altera_avalon_cfi_flash
{
reference_designators = "U5";
}
altera_avalon_epcs_flash_controller
{
reference_designators = "U69";
}
class = "altera_nios_dev_board_cyclone_2c35";
class_version = "6.0";
device_family = "CYCLONEII";
quartus_pgm_file = "system/altera_nios_dev_board_cyclone_2c35.sof";
quartus_project_file = "system/altera_nios_dev_board_cyclone_2c35.qpf";
reference_designators = "U69,U5";
sopc_system_file = "system/altera_nios_dev_board_cyclone_2c35.ptf";
}
RESETS
{
RESET reset_n
{
BOARD_COMPONENT altera_nios_dev_board_cyclone_2c35
{
component_pin = "use_quartus_pin_assignment";
pin_assignment = "";
}
}
}
view_frame_window = "128:128:1024:768";
do_log_history = "0";
}
MODULE cpu
{
class = "altera_nios2";
class_version = "6.0";
iss_model_name = "altera_nios2";
HDL_INFO
{
PLI_Files = "";
Precompiled_Simulation_Library_Files = "";
Simulation_HDL_Files = "";
Synthesis_HDL_Files = "__PROJECT_DIRECTORY__/cpu_test_bench.v, __PROJECT_DIRECTORY__/cpu_mult_cell.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module.v, __PROJECT_DIRECTORY__/cpu_jtag_debug_module_wrapper.v, __PROJECT_DIRECTORY__/cpu.v";
Synthesis_Only_Files = "";
}
MASTER instruction_master
{
PORT_WIRING
{
PORT clk
{
Is_Enabled = "1";
direction = "input";
type = "clk";
width = "1";
}
PORT i_address
{
Is_Enabled = "1";
direction = "output";
type = "address";
width = "26";
}
PORT i_read
{
Is_Enabled = "1";
direction = "output";
type = "read";
width = "1";
}
PORT i_readdata
{
Is_Enabled = "1";
direction = "input";
type = "readdata";
width = "32";
}
PORT i_readdatavalid
{
Is_Enabled = "1";
direction = "input";
type = "readdatavalid";
width = "1";
}
PORT i_waitrequest
{
Is_Enabled = "1";
direction = "input";
type = "waitrequest";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Address_Group = "0";
Has_IRQ = "0";
Irq_Scheme = "individual_requests";
Interrupt_Range = "0-0";
Is_Enabled = "1";
DBS_Big_Endian = "0";
Maximum_Burst_Size = "1";
Burst_On_Burst_Boundaries_Only = "";
Linewrap_Bursts = "";
Interleave_Bursts = "";
Adapts_To = "";
}
}
MASTER tightly_coupled_instruction_master_0
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Is_Instruction_Master = "1";
Has_IRQ = "0";
Is_Enabled = "0";
DBS_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_instruction_master_1
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
DBS_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_instruction_master_2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
DBS_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_instruction_master_3
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Instruction_Master = "1";
Is_Readable = "1";
Is_Writeable = "0";
Has_IRQ = "0";
Is_Enabled = "0";
DBS_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER data_master
{
PORT_WIRING
{
PORT d_address
{
Is_Enabled = "1";
direction = "output";
type = "address";
width = "26";
}
PORT d_byteenable
{
Is_Enabled = "1";
direction = "output";
type = "byteenable";
width = "4";
}
PORT d_irq
{
Is_Enabled = "1";
direction = "input";
type = "irq";
width = "32";
}
PORT d_read
{
Is_Enabled = "1";
direction = "output";
type = "read";
width = "1";
}
PORT d_readdata
{
Is_Enabled = "1";
direction = "input";
type = "readdata";
width = "32";
}
PORT d_waitrequest
{
Is_Enabled = "1";
direction = "input";
type = "waitrequest";
width = "1";
}
PORT d_write
{
Is_Enabled = "1";
direction = "output";
type = "write";
width = "1";
}
PORT d_writedata
{
Is_Enabled = "1";
direction = "output";
type = "writedata";
width = "32";
}
PORT jtag_debug_module_debugaccess_to_roms
{
Is_Enabled = "1";
direction = "output";
type = "debugaccess";
width = "1";
}
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "1";
Irq_Scheme = "individual_requests";
Interrupt_Range = "0-31";
Is_Enabled = "1";
DBS_Big_Endian = "0";
Maximum_Burst_Size = "1";
Burst_On_Burst_Boundaries_Only = "";
Adapts_To = "";
}
}
MASTER data_master2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "1";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "0";
Is_Enabled = "0";
DBS_Big_Endian = "0";
}
}
MASTER tightly_coupled_data_master_0
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "0";
Is_Enabled = "0";
DBS_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_data_master_1
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "0";
Is_Enabled = "0";
DBS_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_data_master_2
{
PORT_WIRING
{
}
SYSTEM_BUILDER_INFO
{
Register_Incoming_Signals = "0";
Bus_Type = "avalon";
Data_Width = "32";
Max_Address_Width = "31";
Address_Width = "8";
Address_Group = "0";
Is_Data_Master = "1";
Is_Readable = "1";
Is_Writeable = "1";
Has_IRQ = "0";
Is_Enabled = "0";
DBS_Big_Endian = "0";
Connection_Limit = "1";
Is_Channel = "1";
}
}
MASTER tightly_coupled_data_master_3
{
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