# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		2c35_fft_acceleration_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F672C6
set_global_assignment -name TOP_LEVEL_ENTITY 2c35_fft_acceleration
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:24:34  APRIL 04, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION 6.0
set_global_assignment -name POST_FLOW_SCRIPT_FILE "quartus_sh:auto_verify_ddr_timing.tcl"
set_global_assignment -name VHDL_FILE "D:/MegaCore/ddr_ddr2_sdram-v3.3.0/lib/auk_ddr_tb_functions.vhd"
set_global_assignment -name VHDL_FILE "D:/MegaCore/ddr_ddr2_sdram-v3.3.0/lib/auk_ddr_functions.vhd"
set_global_assignment -name VHDL_FILE "D:/MegaCore/ddr_ddr2_sdram-v3.3.0/lib/auk_ddr_input_buf.vhd"
set_global_assignment -name VHDL_FILE "D:/MegaCore/ddr_ddr2_sdram-v3.3.0/lib/auk_ddr_timers.vhd"
set_global_assignment -name VHDL_FILE "D:/MegaCore/ddr_ddr2_sdram-v3.3.0/lib/auk_ddr_avalon_if.vhd"
set_global_assignment -name VHDL_FILE "D:/MegaCore/ddr_ddr2_sdram-v3.3.0/lib/auk_ddr_bank_details.vhd"
set_global_assignment -name VHDL_FILE "D:/MegaCore/ddr_ddr2_sdram-v3.3.0/lib/auk_ddr_init.vhd"
set_global_assignment -name USER_LIBRARIES "D:/MegaCore/ddr_ddr2_sdram-v3.3.0/lib;"
set_global_assignment -name BDF_FILE 2c35_fft_acceleration.bdf
set_location_assignment PIN_B13 -to clk_in
set_location_assignment PIN_C5 -to pld_clear_n
set_instance_assignment -name DQS_FREQUENCY "85 MHz" -to ddr_dqs
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1 -to ddr_dm
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1 -to ddr_dqs
set_instance_assignment -name OUTPUT_ENABLE_GROUP 1 -to ddr_dq
set_instance_assignment -name STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS ON -to ddr_dq
set_instance_assignment -name TCO_REQUIREMENT "6 ns" -to clk_to_sdram
set_instance_assignment -name TCO_REQUIREMENT "6 ns" -to clk_to_sdram_n
set_instance_assignment -name TPD_REQUIREMENT "1.75 ns" -from *dq_enable* -to *
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_ras_n
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_cas_n
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_we_n
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_cke[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_a[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_a[1]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_a[2]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_a[3]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_a[4]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_a[5]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_a[6]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_a[7]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_a[8]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_a[9]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_a[10]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_a[11]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_a[12]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_ba[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_ba[1]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_cs_n[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_dm[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_dm[1]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_dq[0]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_dq[1]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_dq[2]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_dq[3]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_dq[4]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_dq[5]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_dq[6]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_dq[7]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_dq[8]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_dq[9]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_dq[10]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_dq[11]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_dq[12]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_dq[13]
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_dq[14]