?? usb.c
字號:
pUSBCtrlAddr->PMR.sus_en = 0;
pUSBCtrlAddr->PMR.sus_mo = 0;
pUSBCtrlAddr->PMR.mcu_res = 0;
pUSBCtrlAddr->PMR.usb_re = 0;
pUSBCtrlAddr->PMR.iso_up = 0;
pUSBCtrlAddr->INDEX.index = 0;
pUSBCtrlAddr->MAXP.maxp = 0x01; //EP0 max packit size = 8
pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
pUSBCtrlAddr->EP0ICSR1.sse_ = 1;
//EP0:clear OUT_PKT_RDY & SETUP_END
pUSBCtrlAddr->INDEX.index = 1;
pUSBCtrlAddr->MAXP.maxp = 0x08; //EP1 max packit size = 64
pUSBCtrlAddr->EP0ICSR1.de_ff = 1;
pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
pUSBCtrlAddr->ICSR2.mode_in = 1;
pUSBCtrlAddr->ICSR2.in_dma_int_en = 1;
pUSBCtrlAddr->ICSR2.iso = 0;
pUSBCtrlAddr->OCSR1.clr_data_tog = 1;
pUSBCtrlAddr->OCSR2.iso = 0;
pUSBCtrlAddr->OCSR2.out_dma_int_en = 1;
pUSBCtrlAddr->INDEX.index = 2;
pUSBCtrlAddr->MAXP.maxp = 0x08; //EP2 max packit size = 64
pUSBCtrlAddr->EP0ICSR1.de_ff = 1;
pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
pUSBCtrlAddr->ICSR2.mode_in = 1;
pUSBCtrlAddr->ICSR2.in_dma_int_en = 1;
pUSBCtrlAddr->ICSR2.iso = 0;
pUSBCtrlAddr->OCSR1.clr_data_tog = 1;
pUSBCtrlAddr->OCSR2.iso = 0;
pUSBCtrlAddr->OCSR2.out_dma_int_en = 1;
pUSBCtrlAddr->INDEX.index = 3;
pUSBCtrlAddr->MAXP.maxp = 0x08; //EP3 max packit size = 64
pUSBCtrlAddr->EP0ICSR1.de_ff = 1;
pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
pUSBCtrlAddr->ICSR2.mode_in = 0;
pUSBCtrlAddr->ICSR2.in_dma_int_en = 0;
pUSBCtrlAddr->ICSR2.iso = 0;
pUSBCtrlAddr->OCSR1.clr_data_tog = 1;
//clear OUT_PKT_RDY, data_toggle_bit.
//The data toggle bit should be cleared when initialization.
pUSBCtrlAddr->OCSR2.iso = 0;
pUSBCtrlAddr->OCSR2.out_dma_int_en = 1;
pUSBCtrlAddr->INDEX.index = 4;
pUSBCtrlAddr->MAXP.maxp = 0x08; //EP4 max packit size = 64
pUSBCtrlAddr->EP0ICSR1.de_ff = 1;
pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
pUSBCtrlAddr->ICSR2.mode_in = 0;
pUSBCtrlAddr->ICSR2.in_dma_int_en = 1;
pUSBCtrlAddr->ICSR2.iso = 0;
pUSBCtrlAddr->OCSR1.clr_data_tog = 1;
//clear OUT_PKT_RDY, data_toggle_bit.
//The data toggle bit should be cleared when initialization.
pUSBCtrlAddr->OCSR2.iso = 0;
pUSBCtrlAddr->OCSR2.out_dma_int_en = 1;
pUSBCtrlAddr->EIR.ep0_int=1;
pUSBCtrlAddr->EIR.ep1_int=1;
pUSBCtrlAddr->EIR.ep2_int=1;
pUSBCtrlAddr->EIR.ep3_int=1;
pUSBCtrlAddr->EIR.ep4_int=1;
pUSBCtrlAddr->UIR.reset_int = 1;
pUSBCtrlAddr->UIR.sus_int = 1;
pUSBCtrlAddr->UIR.resume_int = 1;
//Clear all usbd pending bits
//EP0,1,3 & reset interrupt are enabled
pUSBCtrlAddr->EIER.ep0_int_en = 1;
pUSBCtrlAddr->EIER.ep1_int_en = 1;
pUSBCtrlAddr->EIER.ep3_int_en = 1;
pUSBCtrlAddr->UIER.reset_int_en = 1;
ep0State=EP0_STATE_INIT;
}
#define BIT_ALLMSK (0xffffffff)
#define BIT_USBD (0x1<<25)
#define BIT_DMA2 (0x1<<19)
static void WaitMS22 (DWORD dwMS)
{
volatile DWORD dCount,dwIndex;
for (dwIndex=0;dwIndex<dwMS;dwIndex++) {
for (dCount=0;dCount<100000L;dCount++);
}
}
void Isr_Init(void)
{
volatile S3C2440A_INTR_REG *s2440INT = (S3C2440A_INTR_REG *)OALPAtoVA(S3C2440A_BASE_REG_PA_INTR, FALSE);
volatile S3C2440A_IOPORT_REG *s2440IOP = (S3C2440A_IOPORT_REG *)OALPAtoVA(S3C2440A_BASE_REG_PA_IOPORT, FALSE);
#if 0
s2440IOP->GPGCON &= ~(3<<24);
s2440IOP->GPGCON |= (1<<24); // output
s2440IOP->GPGDN|= (1<<12); // pullup disable
s2440IOP->GPGDAT &= ~(0x1<<12);
#else
s2440IOP->GPDCON &= ~(3<<16);
s2440IOP->GPDCON |= (1<<16); // output
s2440IOP->GPDDN|= (1<<8); // pullup disable
s2440IOP->GPDDAT |= (0x1<<8);
#endif
WaitMS22(10);
//s2440IOP->GPGDAT |= (1<<12); // output
s2440INT->INTMOD=0x0; // All=IRQ mode
s2440INT->INTMSK=BIT_ALLMSK; // All interrupt is masked.
s2440IOP->MISCCR=s2440IOP->MISCCR&~(1<<3); // USBD is selected instead of USBH1
s2440IOP->MISCCR=s2440IOP->MISCCR&~(1<<13); // USB port 1 is enabled.
s2440IOP->GPDDAT &= ~(1<<8); // output
EdbgOutputDebugString("INFO: (unsigned)IsrUsbd : 0x%x\r\n", (unsigned)IsrUsbd);
EdbgOutputDebugString("INFO: (unsigned)IsrHandler : 0x%x\r\n", (unsigned)IsrHandler);
// make value to assemble code "b IsrHandler"
//(*(unsigned *)(0x30000000+0x18)) = 0x330;
pISR =(unsigned)(0xEA000000)+(((unsigned)IsrHandler - (0x80000000 + 0x18 + 0x8) )>>2);
//while(1);
EdbgOutputDebugString("INFO: (pisr pisr pisr pisr): 0x%x\r\n", pISR);
EdbgOutputDebugString("INFO: (pisr pisr pisr pisr): 0x%x\r\n", (&pISR));
// EdbgOutputDebugString("INFO: (unsigned)pISR : 0x%x\r\n", (unsigned)pISR);
s2440INT->SRCPND = BIT_USBD;
if (s2440INT->INTPND & BIT_USBD)
s2440INT->INTPND = BIT_USBD;
s2440INT->INTMSK &= ~BIT_USBD; // USB Interrupt enable.
s2440INT->SRCPND = BIT_DMA2;
if (s2440INT->INTPND & BIT_DMA2)
s2440INT->INTPND = BIT_DMA2;
s2440INT->INTMSK &= ~BIT_DMA2; // DMA Interrupt enable.
}
void IsrUsbd(unsigned int val)
{
U8 saveIndexReg=pUSBCtrlAddr->INDEX.index;
volatile S3C2440A_INTR_REG *s2440INT = (S3C2440A_INTR_REG *)OALPAtoVA(S3C2440A_BASE_REG_PA_INTR, FALSE);
volatile S3C2440A_CLKPWR_REG *s2440PWR = (S3C2440A_CLKPWR_REG *)OALPAtoVA(S3C2440A_BASE_REG_PA_CLOCK_POWER, FALSE);
// EdbgOutputDebugString("INFO : IsrUsbd : Interrupt occurred \r\n");
/*
EdbgOutputDebugString("INFO : IsrUsbd : Interrupt occurred \r\n");
EdbgOutputDebugString("INFO : s2440INT->SRCPND = 0x%x \r\n", s2440INT->SRCPND);
EdbgOutputDebugString("INFO : s2440INT->INTMSK = 0x%x \r\n", s2440INT->INTMSK);
EdbgOutputDebugString("INFO : s2440INT->INTPND = 0x%x \r\n", s2440INT->INTPND);
EdbgOutputDebugString("INFO : s2440PWR->CLKCON = 0x%x \r\n", s2440PWR->CLKCON);
EdbgOutputDebugString("INFO : pUSBCtrlAddr = 0x%x \r\n", pUSBCtrlAddr);
EdbgOutputDebugString("INFO : pUSBCtrlAddr->EIER.ep0_int_en = 0x%x \r\n", pUSBCtrlAddr->EIER.ep0_int_en);
EdbgOutputDebugString("INFO : pUSBCtrlAddr->EIER.ep1_int_en = 0x%x \r\n", pUSBCtrlAddr->EIER.ep1_int_en);
EdbgOutputDebugString("INFO : pUSBCtrlAddr->EIER.ep2_int_en = 0x%x \r\n", pUSBCtrlAddr->EIER.ep2_int_en);
EdbgOutputDebugString("INFO : pUSBCtrlAddr->EIER.ep3_int_en = 0x%x \r\n", pUSBCtrlAddr->EIER.ep3_int_en);
EdbgOutputDebugString("INFO : pUSBCtrlAddr->EIER.ep4_int_en = 0x%x \r\n", pUSBCtrlAddr->EIER.ep4_int_en);
EdbgOutputDebugString("INFO : pUSBCtrlAddr->EIR.ep0_int = 0x%x \r\n", pUSBCtrlAddr->EIR.ep0_int);
EdbgOutputDebugString("INFO : pUSBCtrlAddr->EIR.ep1_int = 0x%x \r\n", pUSBCtrlAddr->EIR.ep1_int);
EdbgOutputDebugString("INFO : pUSBCtrlAddr->EIR.ep2_int = 0x%x \r\n", pUSBCtrlAddr->EIR.ep2_int);
EdbgOutputDebugString("INFO : pUSBCtrlAddr->EIR.ep3_int = 0x%x \r\n", pUSBCtrlAddr->EIR.ep3_int);
EdbgOutputDebugString("INFO : pUSBCtrlAddr->EIR.ep4_int = 0x%x \r\n", pUSBCtrlAddr->EIR.ep4_int);
EdbgOutputDebugString("\r\n");
*/
if (s2440INT->INTPND & BIT_DMA2)
{
DMA2Handler();
goto Exit;
}
if(pUSBCtrlAddr->UIR.sus_int)
{
pUSBCtrlAddr->UIR.sus_int = 1;
EdbgOutputDebugString("<SUS]\r\n");
}
if(pUSBCtrlAddr->UIR.resume_int)
{
pUSBCtrlAddr->UIR.resume_int = 1;
EdbgOutputDebugString("<RSM]\r\n");
}
if(pUSBCtrlAddr->UIR.reset_int)
{
EdbgOutputDebugString("<RSET]\r\n");
ReconfigUsbd();
pUSBCtrlAddr->UIR.reset_int = 1;
PrepareEp1Fifo();
}
if(pUSBCtrlAddr->EIR.ep0_int)
{
//EdbgOutputDebugString("EP0 Interrupt\r\n");
pUSBCtrlAddr->EIR.ep0_int=1;
Ep0Handler();
}
if(pUSBCtrlAddr->EIR.ep1_int)
{
EdbgOutputDebugString("<1:TBD]\r\n");
pUSBCtrlAddr->EIR.ep1_int=1;
Ep1Handler();
}
if(pUSBCtrlAddr->EIR.ep2_int)
{
pUSBCtrlAddr->EIR.ep2_int=1;
EdbgOutputDebugString("<2:TBD]\r\n");
}
if(pUSBCtrlAddr->EIR.ep3_int)
{
EdbgOutputDebugString("<3:TBD]\r\n");
Ep3Handler();
pUSBCtrlAddr->EIR.ep3_int=1;
}
if(pUSBCtrlAddr->EIR.ep4_int)
{
pUSBCtrlAddr->EIR.ep4_int=1;
EdbgOutputDebugString("<4:TBD]\r\n");
}
if (s2440INT->INTPND & BIT_USBD)
{
s2440INT->SRCPND = BIT_USBD;
if (s2440INT->INTPND & BIT_USBD) s2440INT->INTPND = BIT_USBD;
}
Exit:
pUSBCtrlAddr->INDEX.index=saveIndexReg;
}
void Ep3Handler(void)
{
int fifoCnt;
volatile S3C2440A_INTR_REG *s2440INT = (S3C2440A_INTR_REG *)OALPAtoVA(S3C2440A_BASE_REG_PA_INTR, FALSE);
pUSBCtrlAddr->INDEX.index=3;
EdbgOutputDebugString("pUSBCtrlAddr->OCSR1.out_pkt_rdy = 0x%x\r\n", pUSBCtrlAddr->OCSR1.out_pkt_rdy);
if(pUSBCtrlAddr->OCSR1.out_pkt_rdy)
{
fifoCnt=pUSBCtrlAddr->OFCR1.out_cnt_low;
downPt = (LPBYTE)(downPtIndex);
RdPktEp3((U8 *)downPt,fifoCnt);
downPtIndex += 64;
s2440INT->INTMSK |= BIT_USBD; // USB Interrupt disable.
EdbgOutputDebugString("Ep3Handler : downPtIndex = 0x%x\r\n", downPtIndex);
return;
}
//I think that EPO_SENT_STALL will not be set to 1.
if(pUSBCtrlAddr->OCSR1.sent_stall)
{
CLR_EP3_SENT_STALL();
return;
}
}
void DMA2Handler(void)
{
volatile S3C2440A_INTR_REG *s2440INT = (S3C2440A_INTR_REG *)OALPAtoVA(S3C2440A_BASE_REG_PA_INTR, FALSE);
volatile S3C2440A_DMA_REG *v_pDMAregs = (S3C2440A_DMA_REG *)OALPAtoVA(S3C2440A_BASE_REG_PA_DMA, FALSE);
s2440INT->SRCPND = BIT_DMA2;
if (s2440INT->INTPND & BIT_DMA2) s2440INT->INTPND = BIT_DMA2;
downPtIndex += 0x80000;
v_pDMAregs->DIDST2=((U32)downPtIndex+0x80000);
v_pDMAregs->DIDSTC2=(1<<2)|(0<<1)|(0<<0);
v_pDMAregs->DCON2=v_pDMAregs->DCON2&~(0xfffff)|(0x80000);
while(rEP3_DMA_TTC<0xfffff)
{
pUSBCtrlAddr->EP3DTL.ep3_ttl_l = 0xff;
pUSBCtrlAddr->EP3DTM.ep3_ttl_m = 0xff;
pUSBCtrlAddr->EP3DTH.ep3_ttl_h = 0x0f;
}
}
void ConfigEp3DmaMode(U32 bufAddr,U32 count)
{
volatile S3C2440A_INTR_REG *s2440INT = (S3C2440A_INTR_REG *)OALPAtoVA(S3C2440A_BASE_REG_PA_INTR, FALSE);
volatile S3C2440A_DMA_REG *v_pDMAregs = (S3C2440A_DMA_REG *)OALPAtoVA(S3C2440A_BASE_REG_PA_DMA, FALSE);
int i;
pUSBCtrlAddr->INDEX.index=3;
count=count&0xfffff; //transfer size should be <1MB
v_pDMAregs->DISRCC2=(1<<1)|(1<<0);
v_pDMAregs->DISRC2=REAL_PHYSICAL_ADDR_EP3_FIFO; //src=APB,fixed,src=EP3_FIFO
v_pDMAregs->DIDSTC2=(0<<2)|(0<<1)|(0<<0);
v_pDMAregs->DIDST2=bufAddr; //dst=AHB,increase,dst=bufAddr
v_pDMAregs->DCON2=(count)|(1<<31)|(0<<30)|(1<<29)|(0<<28)|(0<<27)|(4<<24)|(1<<23)|(0<<22)|(0<<20);
//handshake,requestor=APB,CURR_TC int enable,unit transfer,
//single service,src=USBD,H/W request,autoreload,byte,CURR_TC
v_pDMAregs->DMASKTRIG2 = (1<<1);
//DMA 2 on
pUSBCtrlAddr->EP3DTL.ep3_ttl_l = 0xff;
pUSBCtrlAddr->EP3DTM.ep3_ttl_m = 0xff;
pUSBCtrlAddr->EP3DTH.ep3_ttl_h = 0x0f;
pUSBCtrlAddr->OCSR2.auto_clr = 1;
pUSBCtrlAddr->OCSR2.out_dma_int_en = 1;
//AUTO_CLR(OUT_PKT_READY is cleared automatically), interrupt_masking.
pUSBCtrlAddr->EP3DU.ep3_unit_cnt = 1;
*(volatile BYTE *)&pUSBCtrlAddr->EP3DC=UDMA_OUT_DMA_RUN|UDMA_DMA_MODE_EN;
// deamnd disable,out_dma_run=run,in_dma_run=stop,DMA mode enable
//wait until DMA_CON is effective.
*(volatile BYTE *)&pUSBCtrlAddr->EP3DC;
for(i=0;i<10;i++);
}
void ConfigEp3IntMode(void)
{
volatile S3C2440A_DMA_REG *v_pDMAregs = (S3C2440A_DMA_REG *)OALPAtoVA(S3C2440A_BASE_REG_PA_DMA, FALSE);
pUSBCtrlAddr->INDEX.index=3;
v_pDMAregs->DMASKTRIG2= (0<<1); // EP3=DMA ch 2
//DMA channel off
pUSBCtrlAddr->OCSR2.auto_clr = 0;
//AUTOCLEAR off,interrupt_enabled (???)
pUSBCtrlAddr->EP3DU.ep3_unit_cnt = 1;
*(volatile BYTE *)&pUSBCtrlAddr->EP3DC=0x0;
//wait until DMA_CON is effective.
*(volatile BYTE *)&pUSBCtrlAddr->EP3DC;
}
#pragma optimize ("",off)
BOOL UbootReadData(DWORD cbData, LPBYTE pbData)
{
volatile S3C2440A_INTR_REG *s2440INT = (S3C2440A_INTR_REG *)OALPAtoVA(S3C2440A_BASE_REG_PA_INTR, FALSE);
volatile S3C2440A_IOPORT_REG *s2440IOP = (S3C2440A_IOPORT_REG *)OALPAtoVA(S3C2440A_BASE_REG_PA_IOPORT, FALSE);
volatile S3C2440A_DMA_REG *v_pDMAregs = (S3C2440A_DMA_REG *)OALPAtoVA(S3C2440A_BASE_REG_PA_DMA, FALSE);
volatile S3C2440A_CLKPWR_REG *s2440PWR = (S3C2440A_CLKPWR_REG *)OALPAtoVA(S3C2440A_BASE_REG_PA_CLOCK_POWER, FALSE);
unsigned int temp;
int i;
volatile unsigned int tPIndex;
Loop:
/*
EdbgOutputDebugString("INFO : UbootReadData : s2440PWR->CLKCON = 0x%x\r\n", s2440PWR->CLKCON);
EdbgOutputDebugString("INFO : UbootReadData : s2440INT->INTMSK = 0x%x\r\n", s2440INT->INTMSK);
EdbgOutputDebugString("INFO : UbootReadData : v_pDMAregs->DCDST2 = 0x%x\r\n", v_pDMAregs->DCDST2);
EdbgOutputDebugString("INFO : UbootReadData : downPtIndex = 0x%x\r\n", downPtIndex);
EdbgOutputDebugString("INFO : UbootReadData : readPtIndex = 0x%x\r\n", readPtIndex);
EdbgOutputDebugString("INFO : UbootReadData : cbData = 0x%x\r\n", cbData);
EdbgOutputDebugString("INFO : UbootReadData : readPtIndex + cbData = 0x%x\r\n", readPtIndex + cbData);
*/
// add by xm.hu
tPIndex = readPtIndex;
#if 0
if(tPIndex==DMABUFFER)
{
EdbgOutputDebugString("tPIndex==DMABUFFER : downPtIndex3 = 0x%x\r\n", downPtIndex);
}
else
{
if (!((tPIndex -DMABUFFER)%832))
{
EdbgOutputDebugString("downPtIndex : downPtIndex3 = 0x%x\r\n", downPtIndex);
EdbgOutputDebugString("readPtIndex : downPtIndex5 = 0x%x\r\n", readPtIndex);
//readPtIndex += 8;
tPIndex +=8;
}
}
#endif
if ( v_pDMAregs->DCDST2 >= readPtIndex + cbData )
// if ( downPtIndex > readPtIndex + cbData )
{
memcpy(pbData, readPtIndex, cbData);
//memcpy(pbData, tPIndex, cbData);
// xm.hu
// EdbgOutputDebugString("UbootReadData %x %x %x %x: +while \r\n",pbData[0],pbData[2],pbData[3],pbData[4]);
readPtIndex += cbData;
loopcnt = 0;
}
else if (loopcnt > 50) // it may be
{
memcpy(pbData, readPtIndex, cbData);
readPtIndex += cbData;
}
else if (downPtIndex == DMABUFFER)
{
while (downPtIndex == DMABUFFER) {
// EdbgOutputDebugString("UbootReadData : downPtIndex = 0x%x\r\n", downPtIndex);
}; // first 64 bytes, get interrupt mode.
// EdbgOutputDebugString("UbootReadData : downPtIndex = 0x%x\r\n", downPtIndex);
#if 1
if ( readPtIndex == DMABUFFER )
{
if (Mylogcnt==0)
{
// xm.hu
//EdbgOutputDebugString("first read ??!!! : +while \r\n");
readPtIndex += 8;
Mylogcnt = 1;
}
//readPtIndex += 8;
//tPIndex = readPtIndex;
//tPIndex += 8;
memcpy(pbData, readPtIndex, cbData);
//memcpy(pbData, tPIndex, cbData);
// xm.hu
//EdbgOutputDebugString("UbootReadData %x %x %x %x: +while \r\n",pbData[0],pbData[2],pbData[3],pbData[4]);
readPtIndex += cbData;
}
#endif
s2440INT->SRCPND = BIT_USBD;
if (s2440INT->INTPND & BIT_USBD) s2440INT->INTPND = BIT_USBD;
s2440INT->INTMSK |= BIT_USBD; // USB Interrupt disable.
// read data with DMA operation.
s2440INT->SRCPND = BIT_DMA2;
if (s2440INT->INTPND & BIT_DMA2) s2440INT->INTPND = BIT_DMA2;
s2440INT->INTMSK &= ~BIT_DMA2; // DMA Interrupt enable.
pUSBCtrlAddr->INDEX.index=3;
CLR_EP3_OUT_PKT_READY();
ConfigEp3DmaMode(downPtIndex,0x80000);
v_pDMAregs->DIDST2=(downPtIndex+0x80000); //for 1st autoreload.
v_pDMAregs->DIDSTC2=(1<<2)|(0<<1)|(0<<0);
v_pDMAregs->DCON2=v_pDMAregs->DCON2&~(0xfffff)|(0x80000);
// EdbgOutputDebugString("UbootReadData : +while \r\n");
// EdbgOutputDebugString("UbootReadData : &(pUSBCtrlAddr->EP3DTL) = 0x%x \r\n", &(pUSBCtrlAddr->EP3DTL));
while(rEP3_DMA_TTC<0xfffff)
{
// EdbgOutputDebugString("UbootReadData : rEP3_DMA_TTC = 0x%x \r\n", rEP3_DMA_TTC);
// EdbgOutputDebugString("INFO : UbootReadData : s2440PWR->CLKCON = 0x%x\r\n", s2440PWR->CLKCON);
// EdbgOutputDebugString("INFO : UbootReadData : v_pDMAregs->DCDST2 = 0x%x\r\n", v_pDMAregs->DCDST2);
pUSBCtrlAddr->EP3DTL.ep3_ttl_l = 0xff;
pUSBCtrlAddr->EP3DTM.ep3_ttl_m = 0xff;
pUSBCtrlAddr->EP3DTH.ep3_ttl_h = 0x0f;
}
// EdbgOutputDebugString("UbootReadData : -while \r\n");
}
else
{
// for (i = 0; i < 60000; i++ )
// {
// }
// loopcnt ++;
// EdbgOutputDebugString("INFO : UbootReadData : loopcnt = 0x%x\r\n", loopcnt);
goto Loop;
}
return TRUE;
}
#pragma optimize ("",on)
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