/* PCI.h - PCI functions header file */  /* Copyright - Galileo technology. */#ifndef __INCpcih#define __INCpcih/* includes */#include"core.h"/* Macros *//* The next Macros configurate the initiator board (SELF) or any any agent on   the PCI to become: MASTER, response to MEMORY transactions , response to   IO transactions or TWO both MEMORY_IO transactions. Those configuration   are for both PCI0 and PCI1. */#define PCI0_MASTER_ENABLE(deviceNumber) pci0WriteConfigReg(                  \          PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE |                \          pci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) )          #define PCI0_MASTER_DISABLE(deviceNumber) pci0WriteConfigReg(                 \          PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE &               \          pci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) )#define PCI1_MASTER_ENABLE(deviceNumber) pci1WriteConfigReg(                  \          PCI_STATUS_AND_COMMAND,deviceNumber,MASTER_ENABLE |                \          pci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) )          #define PCI1_MASTER_DISABLE(deviceNumber) pci1WriteConfigReg(                 \          PCI_STATUS_AND_COMMAND,deviceNumber,~MASTER_ENABLE &               \          pci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) )#define PCI0_MEMORY_ENABLE(deviceNumber) pci0WriteConfigReg(                  \          PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE |                \          pci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) )           #define PCI1_MEMORY_ENABLE(deviceNumber) pci1WriteConfigReg(                  \          PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE |                \          pci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) )#define PCI0_IO_ENABLE(deviceNumber) pci0WriteConfigReg(                      \          PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE |                   \          pci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) )#define PCI1_IO_ENABLE(deviceNumber) pci1WriteConfigReg(                      \          PCI_STATUS_AND_COMMAND,deviceNumber,I_O_ENABLE |                   \          pci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) )#define PCI0_SLAVE_ENABLE(deviceNumber) pci0WriteConfigReg(                   \          PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE |   \          pci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) )#define PCI1_SLAVE_ENABLE(deviceNumber) pci1WriteConfigReg(                   \          PCI_STATUS_AND_COMMAND,deviceNumber,MEMORY_ENABLE | I_O_ENABLE |   \          pci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber) )#define PCI0_DISABLE(deviceNumber) pci0WriteConfigReg(                        \          PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8  &                  \          pci0ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber))#define PCI1_DISABLE(deviceNumber) pci1WriteConfigReg(                        \          PCI_STATUS_AND_COMMAND,deviceNumber,0xfffffff8  &                  \          pci1ReadConfigReg(PCI_STATUS_AND_COMMAND,deviceNumber))#define 	MASTER_ENABLE			BIT2  #define		MEMORY_ENABLE			BIT1  #define		I_O_ENABLE  			BIT0  #define     SELF                    0/* Agent on the PCI bus may have up to 6 BARS. */#define     BAR0                    0x10#define     BAR1                    0x14#define     BAR2                    0x18#define     BAR3                    0x1c#define     BAR4                    0x20#define     BAR5                    0x24/* Defines for the access regions. */#define     PREFETCH_ENABLE                 BIT12#define     PREFETCH_DISABLE                NO_BIT#define     DELAYED_READ_ENABLE             BIT13#define     CACHING_ENABLE                  BIT14/* aggresive prefetch: PCI slave prefetch two burst in advance*/#define     AGGRESIVE_PREFETCH              BIT16 /* read line aggresive prefetch: PCI slave prefetch two burst in advance*/#define     READ_LINE_AGGRESSIVE_PREFETCH   BIT17/* read multiple aggresive prefetch: PCI slave prefetch two burst in advance*/#define     READ_MULTI_AGGRESSIVE_PREFETCH  BIT18#define     MAX_BURST_4                     NO_BIT#define     MAX_BURST_8                     BIT20  /* Bits[21:20] = 01 */#define     MAX_BURST_16                    BIT21  /* Bits[21:20] = 10 */#define     PCI_BYTE_SWAP                   NO_BIT /* Bits[25:24] = 00 */#define     PCI_NO_SWAP                     BIT24  /* Bits[25:24] = 01 */#define     PCI_BYTE_AND_WORD_SWAP          BIT25  /* Bits[25:24] = 10 */#define     PCI_WORD_SWAP                   BIT24 | BIT25 /* Bits[25:24] = 11 */#define     PCI_ACCESS_PROTECT              BIT28#define     PCI_WRITE_PROTECT               BIT29/* typedefs */typedef enum __pciAccessRegions{REGION0,REGION1,REGION2,REGION3,REGION4,REGION5,                                REGION6,REGION7} PCI_ACCESS_REGIONS;typedef enum __pciAgentPrio{LOW_AGENT_PRIO,HI_AGENT_PRIO} PCI_AGENT_PRIO;typedef enum __pciAgentPark{PARK_ON_AGENT,DONT_PARK_ON_AGENT} PCI_AGENT_PARK;typedef enum __pciSnoopType{PCI_NO_SNOOP,PCI_SNOOP_WT,PCI_SNOOP_WB,                            PCI_SNOOP_AND_INVAL_WB} PCI_SNOOP_TYPE;typedef enum __pciSnoopRegion{PCI_SNOOP_REGION0,PCI_SNOOP_REGION1,PCI_SNOOP_REGION2,                              PCI_SNOOP_REGION3} PCI_SNOOP_REGION;typedef struct pciDevice{    char            type[20];    unsigned int    deviceNum;    unsigned int    venID;                                                unsigned int    deviceID;    unsigned int    bar0Base;    unsigned int    bar0Size;    unsigned int    bar0Type;    unsigned int    bar1Base;    unsigned int    bar1Size;    unsigned int    bar1Type;    unsigned int    bar2Base;    unsigned int    bar2Size;    unsigned int    bar2Type;    unsigned int    bar3Base;    unsigned int    bar3Size;    unsigned int    bar3Type;    unsigned int    bar4Base;    unsigned int    bar4Size;    unsigned int    bar4Type;    unsigned int    bar5Base;    unsigned int    bar5Size;    unsigned int    bar5Type;} PCI_DEVICE;typedef struct pciSelfBars{    unsigned int    SCS0Base;    unsigned int    SCS0Size;    unsigned int    SCS1Base;    unsigned int    SCS1Size;    unsigned int    SCS2Base;    unsigned int    SCS2Size;    unsigned int    SCS3Base;    unsigned int    SCS3Size;    unsigned int    internalMemBase;    unsigned int    internalIOBase;    unsigned int    CS0Base;    unsigned int    CS0Size;    unsigned int    CS1Base;    unsigned int    CS1Size;    unsigned int    CS2Base;    unsigned int    CS2Size;    unsigned int    CS3Base;    unsigned int    CS3Size;    unsigned int    CSBootBase;    unsigned int    CSBootSize;    unsigned int    P2PMem0Base;    unsigned int    P2PMem0Size;    unsigned int    P2PMem1Base;    unsigned int    P2PMem1Size;    unsigned int    P2PIOBase;    unsigned int    P2PIOSize;    unsigned int    CPUBase;    unsigned int    CPUSize;} PCI_SELF_BARS;/* read/write configuration registers on local PCI bus. */void pci0WriteConfigReg(unsigned int regOffset,unsigned int pciDevNum,                           unsigned int data);void pci1WriteConfigReg(unsigned int regOffset,unsigned int pciDevNum,                           unsigned int data);unsigned int pci0ReadConfigReg (unsigned int regOffset,                                   unsigned int pciDevNum);unsigned int pci1ReadConfigReg (unsigned int regOffset,                                   unsigned int pciDevNum);/* read/write configuration registers on another PCI bus. */void pci0OverBridgeWriteConfigReg(unsigned int regOffset,                                     unsigned int pciDevNum,                                     unsigned int busNum,unsigned int data);