?? ram.txt
字號:
CS為RAM的片選信號,WR為RAM的寫信號,RD為RAM讀信號,ADR:八位地址信號,Din:八位數據輸入線,Dout為八位數據輸出線。
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RAM is
port (WR: in STD_LOGIC;
RD: in STD_LOGIC;
ADR: in STD_LOGIC_VECTOR (7 downto 0);
CS: in STD_LOGIC;
Din: in STD_LOGIC_VECTOR (7 downto 0);
Dout: out STD_LOGIC_VECTOR (7 downto 0)
);
end RAM;
圖例6 RAM實體
architecture RAM_arch of RAM is
subtype word is std_logic_vector(7 downto 0);
type memory is array (0 to 15)of word;
signal adr_in:integer range 0 to 15;
signal sram:memory;
begin
adr_in<=conv_integer(ADR);
process(wr)begin
if(wr'event and wr='1')then
if(cs='1'and wr='1')then
sram(adr_in)<=din after 2 ns;
end if;
end if;
end process;
process(rd,cs)begin
if(rd='0'and cs='1')then
dout<=sram(adr_in)after 3 ns;
else
dout<="ZZZZZZZZ"after 4 ns;
end if;
end process;
end RAM_arch;
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