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<TD width=64>作 者</TD>
<TD width=233>shixian</TD>
<TD width=63>閱讀次數</TD>
<TD width=85>1539</TD>
<TD width=63>回復次數</TD>
<TD width=85>35</TD></TR>
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<TD width=64>所屬欄目</TD>
<TD width=233>基礎應用與新手入門>> IT英語</TD>
<TD width=63>發表日期</TD>
<TD width=85>2006-9-15</TD>
<TD width=63>回復日期</TD>
<TD
width=85>2006-10-15</TD></TR></TBODY></TABLE></TD></TR></TBODY></TABLE></TD></TR></TBODY></TABLE>
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<DIV class=userInfoBox>積分：2575<BR>第二級</DIV>
<DIV class=userInfoBox>注冊時間<BR>2006-6-12</DIV></DIV></TD>
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<DIV class=TitleInfoBox align=right>發表時間：2006-9-15 8:39:55 樓主</DIV>
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<DIV id=cont_right style="WIDTH: 495px">REDUCED INSTRUCTION <BR>SET
COMPUTERS <BR><BR>Studies of the execution behavior of high-level language
programs have provided guidance in designing a new type of processor
architecture：the reduced instruction set computer（RISC）．Assignment
statements predominate，suggesting that the simple movement of data should
be optimized．There are also many IF and LOOP instructions，which suggest
that the underlying sequence control mechanism needs to be optimized to
permit efficient pipelining．Studies of operand reference patterns suggest
that it should be possible to enhance performance by keeping a moderate
number of operands in registers． <BR>These studies have motivated the key
characteristics of RISC machines：（1）a limited instruction set with a fixed
format．（2）a large number of registers or the use of a compiler that
optimizes register usage，and（3）an emphasis on optimizing the instruction
pipeline． <BR>The simple instruction set of a RISC lends itself to
efficient pipelining because there are fewer and more predictable
operations performed per instruction．[1] A RISC instruction set
architecture also lends itself to the delayed branch technique，in which
branch instructions are rearranged with other instructions to improve
pipeline efficiency． <BR>Although RISC systems have been defined and
designed in a variety of ways by different groups，the key elements shared
by most designs are these： <BR>．A large number of general-purpose
registers，or the use of compiler technology to optimize register usage
<BR>．A limited and simple instruction set <BR>．An emphasis on optimizing
the instruction pipeline <BR>Table 2-1 compares several RISC and non-RISC
systems. <BR><BR>1．Instruction Execution Characteristics <BR><BR>To
understand the line of reasoning of the RISC advocates，we begin with a
brief review of instruction execution characteristics．The aspects of
computation of interest are as follows： <BR>• Operations performed：These
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