?? can.lst
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C51 COMPILER V7.02a CAN 08/31/2006 08:52:05 PAGE 7
362 // 0: No Error
363 // 1: Stuff Error: 位填充錯誤
364 // 2: Form Error: 接收幀格式錯誤
365 // 3: AckError: 對方接收CAN控制器無應(yīng)答
366 // 4: Bit1Error: 發(fā)送隱性電平“1”，監(jiān)測為“0”
367 // 5: Bit0Error: 發(fā)送顯性電平“0”，監(jiān)測為“1”，應(yīng)答錯誤等
368 // 6: CRCError: 接收數(shù)據(jù)的CRC校驗碼錯誤
369 // 7: Unused: 無CAN事件發(fā)生
370
371 CAN0TST / CANTEST // Test Register
372 // Bit7: Rx: Monitors the actual value of the CAN_RX Pin; 0/1 <==> CAN_RX.
373 // BIt[6..5]: Tx1-0: Control of CAN_TX pin
374 // 00: Reset value, CAN_TX is controlled by the CAN Core.
375 // 01: Sample Point can be monitored at CAN_TX pin.
376 // 10: CAN_TX pin drives a dominant (‘0’) value.
377 // 11: CAN_TX pin drives a recessive (‘1’) value.
378 // Bit4: 0/1: Loop Back Mode is Disabled / Enabled.
379 // Bit3: 0/1: Normal / Silent Silent Mode
380 // Bit2: 0/1: Basic Mode Is Disabled / Enabled.
381 // In Basic Mode, IF1 Used as Tx Buffer, IF2 Used as Rx Buffer.
382
383 ERRCNT // Error Counter
384 // Bit15: RP: Receive Error Passive; 0/1: Below / Reached the error passivelevel
385 // Bit[14..]: REC[6..0] Receive Error Counter,Values between 0 and 127.
386 // Bit[7..0]: TEC[7..0] Transmit Error Counter,Values between 0 and 255.
387
388 BITREG // Bit Timing Register.
389 // Bit[14..12]: TSeg2, the time segment AFTER the sample point, 0x01-0x07.
390 // Bit[11..8]: TSeg1, the time segment BEFORE the sample point, 0x01-0x0F.
391 // Bit[7..6]: SJW, (Re)Synchronisation Jump Width, 0x00-0x03.
392 // Bit[5..0]: BRP, Baud Rate Prescaler, 0x01-0x3F.
393
394 BRPEXT // BRP Extension Register.
395 // Bit[3..0]: BRPE, Baud Rate Prescaler Extension, 0x00-0x0F.
396 // Baud Rate Prescaler = BRPE(MSBs) | BRP (LSBs).
397
398 INTREG // Interrupt Register.
399 // BIt[15..8]: IntId[15..0],
400 // 0x0000 No interrupt is pending.
401 // 0x0001-0x0020 Number of Message Object which caused the interrupt.
402 // 0x0021-0x7FFF unused.
403 // 0x8000 Status Interrupt.
404 // 0x8001-0xFFFF unused
405
406 /////////////////////////////////////////////////////////////////////////////
407 // Message Interface Register Sets //
408 /////////////////////////////////////////////////////////////////////////////
409 IF1CMDRQST // IF1 Command Request Registers.
410 // Bit15: Busy Busy Flag. Set to '1' when writing to the IFx Command Request Register
411 // Reset to '0' when read/write action has finished.
412 // Bit[5..0]: Message Number
413 // 0x01-0x20 Valid Message Number.
414 // 0x00 Not a valid Message Number, interpreted as 0x20.
415 // 0x21-0x3F Not a valid Message Number, interpreted as 0x01-0x1F.
416
417 IF1CMDMSK // IF1 Command Mask Registers.
418 // Bit7: WR/RD, 0/1: Write/Read.
419
420 // If Direction = Write.
421 // Bit6: Mask, 0/1: Mask bits unchanged / Transfer Identifier Mask + MDir + MXtd to Message Object.
422 // Bit5: Arb, 0/1: Arb bits unchanged / Transfer Identifier + Dir + Xtd + MsgVal to Message Object.
423 // Bit4: Control, 0/1: Control Bits unchanged / Transfer Control Bits to Message Object.
C51 COMPILER V7.02a CAN 08/31/2006 08:52:05 PAGE 8
424 // Bit3: ClrIntPnd, When writing to a Message Object, this bit is ignored.
425 // Bit2: TxRqst/NewDat, 0/1: TxRqst bit unchanged / Set TxRqst bit.
426 // Bit1: Data A, 0/1: Data Bytes0-3 unchanged / Transfer Data Bytes0-3 to Message Object.
427 // Bit0: Data B, 0/1: Data Bytes4-7 unchanged / Transfer Data Bytes4-7 to Message Object.
428
429 // If Direction = Read.
430 // Bit6: Mask, 0/1: Mask bits unchanged / Transfer Identifier Mask + MDir + MXtd to IFx Message Buffer
-Register.
431 // Bit5: Arb, 0/1: Arb bits unchanged / Transfer Identifier + Dir + Xtd + MsgVal to IFx Message Buffe
-r Register.
432 // Bit4: Control, 0/1: Control Bits unchanged / Transfer Control Bits to IFx Message Buffer Register.
433 // Bit3: ClrIntPnd: 0/1: IntPnd bit remains unchanged / Clear IntPnd bit in the Message Object.
434 // Bit2: TxRqst/NewDat: 0/1: NewDat bit remains unchanged / Clear NewDat bit in the Message Object.
435 // Bit1: Data A, 0/1: Data Bytes 0-3 unchanged / Transfer Data Bytes 0-3 to IFx Message Buffer Register
-.
436 // Bit0: Data B, 0/1: Data Bytes 4-7 unchanged / Transfer Data Bytes 4-7 to IFx Message Buffer Register
-.
437
438 IF1MSK1 // IF1 Mask 1 Registers
439 // Bit[15..0]: Msk[15..0].
440 IF1MSK2 // IF1 Mask 2 Registers
441 // Bit15: MXtd = 1: The extended identifier bit (IDE) is used for acceptance filtering.
442 // Bit14: MDir.
443 // Bit[12..0]: Msk[28..16].
444
445 IF1ARB1 // IF1 Arbitration 1 Registers
446 // Bit[15..0]: ID[15..0].
447 IF1ARB2 // IF1 Arbitration 2 Registers
448 // Bit15: MsgVal = 1: Message is Valid.
449 // Bit14: Xtd = 1: The 29-bit Identifier will be used.
450 // Bit13: Dir.
451 // Bit[12..0]: ID[28..16].
452
453 IF1MSGC // IF1 Message Control Registers
454 // Bit15: NewDat:
455 // Bit14: MsgLst:
456 // Bit13: IntPnd:
457 // Bit12: UMask:
458 // Bit11: TxIE:
459 // Bit10: RxIE:
460 // Bit9: RmtEn:
461 // Bit8: TxRqst:
462 // Bit7: EoB:
463 // Bit[3..0]: DLC[3..0].
464
465
466 // Message Object Structure.
467 // UMask Msk28-0 MXtd MDir EoB NewDat MsgLst RxIE TxIE IntPnd RmtEn TxRqst
468 // MsgVal ID28-0 Xtd Dir DLC3-0 Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7
469
470 // MsgVal: Message Valid
471 // 1: The Message Object is configured and should be considered by the Message Handler.
472 // 0: The Message Object is ignored by the Message Handler.
473 // UMask: Use Acceptance Mask
474 // 1: Use Mask (Msk28-0, MXtd, and MDir) for acceptance filtering
475 // 0: Mask ignored.
476 // ID[28..0]: Message Identifier
477 // ID[28..0]: 29-bit Identifier (“Extended Frame”).
478 // ID[28..18]: 11-bit Identifier (“Standard Frame”).
479 // Msk[28..0]: Identifier Mask
480 // 1: The corresponding identifier bit is used for acceptance filtering.
481 // 0: The corresponding bit in the identifier of the message object cannot inhibit the match in the a
C51 COMPILER V7.02a CAN 08/31/2006 08:52:05 PAGE 9
-cceptance filtering.
482 // Xtd: Extended Identifier Enabiled(1) / Disabled(0).
483 // MXtd: Mask Extended Identifier Enabiled(1) / Disabled(0).
484 // Dir: Message Direction, 0/1: Receive / Transmit.
485 // MDir: Mask Message Direction, 0/1: No effect / Acceptance filtering
486 // EoB: End of Buffer, 0/1: MsgOBJ Isn't / Is the Last Message of FIFO.
487 // NewDat: New Data(1).
488 // MsgLst: Message Lost(1).
489 // RxIE: Receive Interrupt Enable(1) or Disable(0).
490 // TxIE: Transmit Interrupt Enable(1) or Disable(0).
491 // IntPnd: Interrupt Pending. This message object isn't / is the source of an interrupt.
492 // RmtEn: Remote Enable(1), At the reception of a Remote Frame, TxRqst is set.
493 // TxRqst: Transmit Request(1), The transmission is not yet done.
494 // DLC[3..0]: Data Length Code
495 // 0..8: Data Frame has 0..8 data bytes.
496 // 9..15: Data Frame has 8 data bytes
497
498 TRANSREQ1 // Transmission Request Registers 1. <Read Only>
499 // Bit[15..8]: TxRqst[16..9].
500 // Bit[7..0]: TxRqst[8..0].
501 TRANSREQ2 // Transmission Request Registers 2. <Read Only>
502 // Bit[31..24]: TxRqst[32..25].
503 // Bit[23..16]: TxRqst[24..17].
504
505 NEWDAT1 // New Data Registers 1. <Read Only>
506 // Bit[15..8]: NewDat[16..9].
507 // Bit[7..0]: NewDat[8..0].
508 NEWDAT2 // New Data Registers 2. <Read Only>
509 // Bit[31..24]: NewDat[32..25].
510 // Bit[23..16]: NewDat[24..17].
511
512 INTPEND1 // Interrupt Pending Registers 1. <Read Only>
513 // Bit[15..8]: IntPnd[16..9].
514 // Bit[7..0]: IntPnd[8..0].
515 INTPEND2 // Interrupt Pending Registers 2. <Read Only>
516 // Bit[31..24]: IntPnd[32..25].
517 // Bit[23..16]: IntPnd[24..17].
518
519 MSGVAL1 // Message Valid 1 Register 1. <Read Only>
520 // Bit[15..8]: MsgVal[16..9].
521 // Bit[7..0]: MsgVal[8..0].
522 MSGVAL2 // Message Valid 1 Register 2. <Read Only>
523 // Bit[31..24]: MsgVal[32..25].
524 // Bit[23..16]: MsgVal[24..17].
525
526 */
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 126 ----
CONSTANT SIZE = ---- ----
XDATA SIZE = 16 ----
PDATA SIZE = ---- ----
DATA SIZE = ---- 14
IDATA SIZE = ---- ----
BIT SIZE = ---- ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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