#define TIM1_TOIE         (Tim1_C1 * 8 + 7 - 5)
#define TIM1_FOLV2        (Tim1_C1 * 8 + 7 - 4)
#define TIM1_FOLV1        (Tim1_C1 * 8 + 7 - 3)
#define TIM1_OLVL2        (Tim1_C1 * 8 + 7 - 2)
#define TIM1_IEDG1        (Tim1_C1 * 8 + 7 - 1)
#define TIM1_OLVL1        (Tim1_C1 * 8 + 7 - 0)

/* ------Timer 1 Status Register------ */

#define TIM1_ICF1         (Tim1_S * 8 + 7 - 7)
#define TIM1_OCF1         (Tim1_S * 8 + 7 - 6)
#define TIM1_TOF          (Tim1_S * 8 + 7 - 5)
#define TIM1_ICF2         (Tim1_S * 8 + 7 - 4)
#define TIM1_OCF2         (Tim1_S * 8 + 7 - 3)

/* -----Timer 2 Control Register 2---- */

#define TIM2_TCM1E        (Tim2_C2 * 8 + 7 - 7)
#define TIM2_TCM2E        (Tim2_C2 * 8 + 7 - 6)
#define TIM2_OPM          (Tim2_C2 * 8 + 7 - 5)
#define TIM2_PWM          (Tim2_C2 * 8 + 7 - 4)
#define TIM2_CC1          (Tim2_C2 * 8 + 7 - 3)
#define TIM2_CC0          (Tim2_C2 * 8 + 7 - 2)
#define TIM2_IEDG2        (Tim2_C2 * 8 + 7 - 1)
#define TIM2_EXEDG        (Tim2_C2 * 8 + 7 - 0)

/* -----Timer 2 Control Register 1---- */

#define TIM2_ICIE         (Tim2_C1 * 8 + 7 - 7)
#define TIM2_OCIE         (Tim2_C1 * 8 + 7 - 6)
#define TIM2_TOIE         (Tim2_C1 * 8 + 7 - 5)
#define TIM2_FOLV2        (Tim2_C1 * 8 + 7 - 4)
#define TIM2_FOLV1        (Tim2_C1 * 8 + 7 - 3)
#define TIM2_OLVL2        (Tim2_C1 * 8 + 7 - 2)
#define TIM2_IEDG1        (Tim2_C1 * 8 + 7 - 1)
#define TIM2_OLVL1        (Tim2_C1 * 8 + 7 - 0)

/* ------Timer 2 Status Register------ */

#define TIM2_ICF1         (Tim2_S * 8 + 7 - 7)
#define TIM2_OCF1         (Tim2_S * 8 + 7 - 6)
#define TIM2_TOF          (Tim2_S * 8 + 7 - 5)
#define TIM2_ICF2         (Tim2_S * 8 + 7 - 4)
#define TIM2_OCF2         (Tim2_S * 8 + 7 - 3)


/* ----ADC Control/Status Register---- */
#define ADC_COCO          (Adc_C * 8 + 7 - 7)
#define ADC_ADON          (Adc_C * 8 + 7 - 5)

/* ------MCC Control/Status Register------ */
#define MCO	7
#define SMS	4

/*--------------------------------------------------------------------------
        ST72321 I/O Port Registers
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_PA
extern volatile unsigned char PA_DR;    /* port A data register            */
extern          unsigned char PA_DDR;   /*        data direction register  */
extern          unsigned char PA_OR;    /*        option register          */

#pragma DATA_SEG SHORT ST7_PB
extern volatile unsigned char PB_DR;    /* port B data register            */
extern          unsigned char PB_DDR;   /*        data direction regiater  */
extern          unsigned char PB_OR;    /*        option register          */
                                                                 
#pragma DATA_SEG SHORT ST7_PC
extern volatile unsigned char PC_DR;    /* port C data register            */
extern          unsigned char PC_DDR;   /*        data direction option    */
extern          unsigned char PC_OR;    /*        option register          */

#pragma DATA_SEG SHORT ST7_PD
extern volatile unsigned char PD_DR;    /* port D data register            */
extern          unsigned char PD_DDR;   /*        data direction register  */
extern          unsigned char PD_OR;    /*        option register          */

#pragma DATA_SEG SHORT ST7_PE
extern volatile unsigned char PE_DR;    /* port E data register            */
extern          unsigned char PE_DDR;   /*        data direction register  */
extern          unsigned char PE_OR;    /*        option register          */

#pragma DATA_SEG SHORT ST7_PF
extern volatile unsigned char PF_DR;    /* port F data register            */
extern          unsigned char PF_DDR;   /*        data direction register  */
extern          unsigned char PF_OR;    /*        option register          */

/*--------------------------------------------------------------------------
        ST72321 I2C Internal Registers
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_I2C
extern volatile unsigned char I2CCR;           // Control Register
extern volatile unsigned char I2CSR1;          // Status Register 1
extern volatile unsigned char I2CSR2;          // Status Register 2
extern volatile unsigned char I2CCCR;          // Clock Control Register
extern volatile unsigned char I2COAR1;         // Own Address Register 1 
extern volatile unsigned char I2COAR2;         // Own Address Register 2 
extern volatile unsigned char I2CDR;           // I2C Data Register

/*--------------------------------------------------------------------------
        ST72321 SPI Internal Registers
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_SPI
extern volatile unsigned char SPI1_DR;         /* data register                   */
extern volatile unsigned char SPI1_CR;         /* control register                */
extern volatile unsigned char SPI1_SR;         /* status register                 */
                                                                    
/*--------------------------------------------------------------------------
        ST72321 ITC Internal Registers
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_ITC
extern volatile unsigned char ISPR0;          /* interrupt software priority reg0*/
extern volatile unsigned char ISPR1;          /* interrupt software priority reg1*/
extern volatile unsigned char ISPR2;          /* interrupt software priority reg2*/
extern volatile unsigned char ISPR3;          /* interrupt software priority reg3*/
extern volatile unsigned char EICR;            // External Interrupt Control Register

/*--------------------------------------------------------------------------
        ST72321 Flash control/status reg
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_FLASH
extern volatile unsigned char FCSR;            // Flash Control status reg     


/*--------------------------------------------------------------------------
        ST72321 WATCHDOG reg
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_WDG
extern volatile unsigned char WDGCR;          /* WatchDog Control Register         */
extern volatile unsigned char SICSR;          // System Integrity Control/Status  Register  


/*--------------------------------------------------------------------------
        ST72321 Main Clock control/status reg
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_MCC
extern volatile unsigned char MCCSR;          // Main clock control/status reg     
extern volatile unsigned char MCCBCR;         // Main clock cntrl/beep control reg     

/*--------------------------------------------------------------------------
        ST72321 Timer A Internal Registers
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_TIMA
extern volatile unsigned char TIM1_CR2;         /* control register 2      */
extern volatile unsigned char TIM1_CR1;         /* control register 1      */
extern volatile unsigned char TIM1_SR;          /* status register         */
extern volatile unsigned char TIM1_IC1H;        /* input capture 1 high    */
extern volatile unsigned char TIM1_IC1L;        /* input capture 1 low     */
extern volatile unsigned char TIM1_OC1H;        /* output compare 1 high   */
extern volatile unsigned char TIM1_OC1L;        /* output compare 1 low    */
extern volatile unsigned char TIM1_CNT;         /* counter high            */
extern volatile unsigned char TIM1_CNTL;        /* counter low             */
extern volatile unsigned char TIM1_ACH;         /* alternate counter high  */
extern volatile unsigned char TIM1_ACL;         /* alternate counter low   */
extern volatile unsigned char TIM1_IC2H;        /* input capture 2 high    */
extern volatile unsigned char TIM1_IC2L;        /* input capture 2 low     */
extern volatile unsigned char TIM1_OC2H;        /* output compare 2 high   */
extern volatile unsigned char TIM1_OC2L;        /* output compare 2 low    */


/*--------------------------------------------------------------------------
        ST72321 Timer B Internal Registers
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_TIMB
extern volatile unsigned char TIM2_CR2;         /* control register 2      */
extern volatile unsigned char TIM2_CR1;         /* control register 1      */
extern volatile unsigned char TIM2_SR;          /* status register         */
extern volatile unsigned char TIM2_IC1H;        /* input capture 1 high    */
extern volatile unsigned char TIM2_IC1L;        /* input capture 1 low     */
extern volatile unsigned char TIM2_OC1H;        /* output compare 1 high   */
extern volatile unsigned char TIM2_OC1L;        /* output compare 1 low    */
extern volatile unsigned char TIM2_CNT;         /* counter high            */
extern volatile unsigned char TIM2_CNTL;        /* counter low             */
extern volatile unsigned char TIM2_ACH;         /* alternate counter high  */
extern volatile unsigned char TIM2_ACL;         /* alternate counter low   */
extern volatile unsigned char TIM2_IC2H;        /* input capture 2 high    */
extern volatile unsigned char TIM2_IC2L;        /* input capture 2 low     */
extern volatile unsigned char TIM2_OC2H;        /* output compare 2 high   */
extern volatile unsigned char TIM2_OC2L;        /* output compare 2 low    */

/*--------------------------------------------------------------------------
        ST72321 SCI Internal Registers
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_SCI
extern volatile unsigned char SCI_SCSR;         /* status register         */     
extern volatile unsigned char SCI_SCDR;         /* data register           */
extern volatile unsigned char SCI_SCBRR;        /* baud rate register      */
extern volatile unsigned char SCI_SCCR1;        /* control register 1      */
extern volatile unsigned char SCI_SCCR2;        /* control register 2      */
extern volatile unsigned char SCI_PSCBRR;       /* rx baud rate register   */
extern volatile unsigned char SCI_PRETEST;      /* reserved                */
extern volatile unsigned char SCI_PSCBRT;       /* tx baud rate register   */


/*--------------------------------------------------------------------------
        ST72321 ADC Internal Registers
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_ADC
//extern volatile unsigned char ADCCSR;          // control/status register        
extern volatile unsigned char ADC_CR;           /* control/status register */
extern volatile unsigned char ADC_DR;           /* data register           */
//extern volatile unsigned char ADCDRH;          // data high register        
extern volatile unsigned char ADCDRL;          // data low register        
                                                    
                                                    
/*--------------------------------------------------------------------------
        ST72321 PWM ART Internal Registers
---------------------------------------------------------------------------*/
#pragma DATA_SEG SHORT ST7_PWMART
extern volatile unsigned char PWMDCR3;         // PWM AR duty cycle register 3    
extern volatile unsigned char PWMDCR2;         // PWM AR duty cycle register 2    
extern volatile unsigned char PWMDCR1;         // PWM AR duty cycle register 1    
extern volatile unsigned char PWMDCR0;         // PWM AR duty cycle register 0    
extern volatile unsigned char PWMCR;           // PWM AR timer cntrl register     
extern volatile unsigned char ARTCSR;          // autoreload timer cntrl status reg
extern volatile unsigned char ARTCAR;          // autoreload timer counter access reg
extern volatile unsigned char ARTARR;          // autoreload timer autoreload reg 
extern volatile unsigned char ARTICCSR;        // AR timer input capture control/status reg 
extern volatile unsigned char ARTICR1;         // AR timer input capture reg 1
extern volatile unsigned char ARTICR2;         // AR timer input capture reg 2 

#pragma DATA_SEG DEFAULT

/******************************* end of file **********************************/