/*********************************************************************
 *
 * Copyright:
 *	1999-2000 MOTOROLA, INC. All Rights Reserved.  
 *  You are hereby granted a copyright license to use, modify, and
 *  distribute the SOFTWARE so long as this entire notice is
 *  retained without alteration in any modified and/or redistributed
 *  versions, and that such modified versions are clearly identified
 *  as such. No licenses are granted by implication, estoppel or
 *  otherwise under any patents or trademarks of Motorola, Inc. This 
 *  software is provided on an "AS IS" basis and without warranty.
 *
 *  To the maximum extent permitted by applicable law, MOTOROLA 
 *  DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING 
 *  IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
 *  PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE 
 *  SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY 
 *  ACCOMPANYING WRITTEN MATERIALS.
 * 
 *  To the maximum extent permitted by applicable law, IN NO EVENT
 *  SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING 
 *  WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS 
 *  INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
 *  LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.   
 * 
 *  Motorola assumes no responsibility for the maintenance and support
 *  of this software
 ********************************************************************/

/*
 * File:		sysinit.c
 * Purpose:		Reset configuration of the M5282EVB
 */

#include "mcf5282.h"
#include "init.h"
#include <stdio.h>
/********************************************************************/

void mcf5282_uart_init(void);
void mcf5282_pll_init(void);


void
mcf5282_init(void)
{
	void mcf5282_wtm_init(void);
	void mcf5282_scm_init(void);
	void mcf5282_cs_init(void);
	void mcf5282_sdram_init(void);
	
	extern char __DATA_ROM[];
	extern char __DATA_RAM[];
	extern char __DATA_END[];
	extern char __BSS_START[];
	extern char __BSS_END[];
	extern uint32 VECTOR_TABLE[];
	extern uint32 __VECTOR_RAM[];
	register uint32 n;
	register uint8 *dp, *sp;

    MCF5282_GPIO_PBCDPAR = 0xC0; /* Get access to SDRAM */


	mcf5282_wtm_init();
	mcf5282_pll_init();
	mcf5282_scm_init();
	mcf5282_uart_init();
	mcf5282_cs_init();
	mcf5282_sdram_init();
	
	/* Turn Instruction Cache ON */
/*
	mcf5xxx_wr_cacr(0
		| MCF5XXX_CACR_CENB
		| MCF5XXX_CACR_CINV
		| MCF5XXX_CACR_DISD
		| MCF5XXX_CACR_CEIB
		| MCF5XXX_CACR_CLNF_00);
... and I'm turning it OFF - Scott Mauer */
		
	/* Copy the vector table to RAM */
	if (__VECTOR_RAM != VECTOR_TABLE)
	{
		for (n = 0; n < 256; n++)
			__VECTOR_RAM[n] = VECTOR_TABLE[n];
	}
    mcf5xxx_wr_vbr((uint32)__VECTOR_RAM);

	/* 
	 * Move initialized data from ROM to RAM. 
	 */
	if (__DATA_ROM != __DATA_RAM)
	{
		dp = (uint8 *)__DATA_RAM;
		sp = (uint8 *)__DATA_ROM;
		n = __DATA_END - __DATA_RAM;
		while (n--)
			*dp++ = *sp++;
	}
 
	/* 
	 * Zero uninitialized data 
	 */
	if (__BSS_START != __BSS_END)
	{
		sp = (uint8 *)__BSS_START;
		n = __BSS_END - __BSS_START;
		while (n--)
			*sp++ = 0;
	}
}

/********************************************************************/
/* #pragma overload void __initialize_hardware(void); */
/* Called by Metrowerks Runtime to initialize UARTs */
void __initialize_hardware(void)
{
mcf5282_pll_init();
mcf5282_uart_init();
}


/********************************************************************/

/********************************************************************/
void 
mcf5282_wtm_init(void)
{
	/*
	 * Disable Software Watchdog Timer
	 */
	MCF5282_WTM_WCR = 0;
}
/********************************************************************/
void 
mcf5282_pll_init(void)
{
	/*
	 * Multiply 8Mhz reference crystal by 8 to acheive system clock of 64Mhz
	 */
	MCF5282_CLOCK_SYNCR = MCF5282_CLOCK_SYNCR_MFD(2);
	
	while (!(MCF5282_CLOCK_SYNSR & MCF5282_CLOCK_SYNSR_LOCK));
}
/****************************************************************/
void
mcf5282_scm_init(void)
{
	/* 
	 * Enable on-chip modules to access internal SRAM 
	 */
	MCF5282_SCM_RAMBAR = (0 
		|	MCF5282_SCM_RAMBAR_BA(SRAM_ADDRESS)
		|	MCF5282_SCM_RAMBAR_BDE);
}
/********************************************************************/
void
mcf5282_uart_init(void)
{
	/*
	 * Initialize all three UARTs for serial communications
	 */
 
	register uint16 ubgs;

	/*
	 * Set Port UA to initialize URXD0/URXD1 UTXD0/UTXD1 
	 */
	MCF5282_GPIO_PUAPAR = 0x0F;

	/*
	 * Reset Transmitter 
	 */
	MCF5282_UART0_UCR = MCF5282_UART_UCR_RESET_TX;
	MCF5282_UART1_UCR = MCF5282_UART_UCR_RESET_TX;
	MCF5282_UART2_UCR = MCF5282_UART_UCR_RESET_TX;

	/* 
	 * Reset Receiver 
	 */
	MCF5282_UART0_UCR = MCF5282_UART_UCR_RESET_RX;
	MCF5282_UART1_UCR = MCF5282_UART_UCR_RESET_RX;
	MCF5282_UART2_UCR = MCF5282_UART_UCR_RESET_RX;

	/* 
	 * Reset Mode Register 
	 */	
	MCF5282_UART0_UCR = MCF5282_UART_UCR_RESET_MR;
	MCF5282_UART1_UCR = MCF5282_UART_UCR_RESET_MR;
	MCF5282_UART2_UCR = MCF5282_UART_UCR_RESET_MR;

	/*
	 * No parity, 8-bits per character 
	 */
	MCF5282_UART0_UMR = (0
		| MCF5282_UART_UMR1_PM_NONE
		| MCF5282_UART_UMR1_BC_8 );
	MCF5282_UART1_UMR = (0
		| MCF5282_UART_UMR1_PM_NONE
		| MCF5282_UART_UMR1_BC_8 );
	MCF5282_UART2_UMR = (0
		| MCF5282_UART_UMR1_PM_NONE
		| MCF5282_UART_UMR1_BC_8 );

	/*
	 * No echo or loopback, 1 stop bit 
	 */
	MCF5282_UART0_UMR = (0
		| MCF5282_UART_UMR2_CM_NORMAL
		| MCF5282_UART_UMR2_STOP_BITS_1);
	MCF5282_UART1_UMR = (0
		| MCF5282_UART_UMR2_CM_NORMAL
		| MCF5282_UART_UMR2_STOP_BITS_1);
	MCF5282_UART2_UMR = (0
		| MCF5282_UART_UMR2_CM_NORMAL
		| MCF5282_UART_UMR2_STOP_BITS_1);

	/*
	 * Set Rx and Tx baud by timer 
	 */
	MCF5282_UART0_UCSR = (0
		| MCF5282_UART_UCSR_RCS_SYS_CLK
		| MCF5282_UART_UCSR_TCS_SYS_CLK);
	MCF5282_UART1_UCSR = (0
		| MCF5282_UART_UCSR_RCS_SYS_CLK
		| MCF5282_UART_UCSR_TCS_SYS_CLK);
	MCF5282_UART2_UCSR = (0
		| MCF5282_UART_UCSR_RCS_SYS_CLK
		| MCF5282_UART_UCSR_TCS_SYS_CLK);
	
	/*
	 * Mask all UART interrupts 
	 */
	MCF5282_UART0_UIMR = 0;
	MCF5282_UART1_UIMR = 0;
	MCF5282_UART2_UIMR = 0;

	/*
	 * Calculate baud settings 
	 */
	ubgs = (uint16)((SYSTEM_CLOCK*1000000)/(UART_BAUD * 32));

	MCF5282_UART0_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
	MCF5282_UART0_UBG2 = (uint8)(ubgs & 0x00FF);
	MCF5282_UART1_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
	MCF5282_UART1_UBG2 = (uint8)(ubgs & 0x00FF);
	MCF5282_UART2_UBG1 = (uint8)((ubgs & 0xFF00) >> 8);
	MCF5282_UART2_UBG2 = (uint8)(ubgs & 0x00FF);

	/* 
	 * Enable receiver and transmitter 
	 */
	MCF5282_UART0_UCR = (0
		| MCF5282_UART_UCR_TX_ENABLED
		| MCF5282_UART_UCR_RX_ENABLED);
	MCF5282_UART1_UCR = (0
		| MCF5282_UART_UCR_TX_ENABLED
		| MCF5282_UART_UCR_RX_ENABLED);
	MCF5282_UART2_UCR = (0
		| MCF5282_UART_UCR_TX_ENABLED
		| MCF5282_UART_UCR_RX_ENABLED);
}
/********************************************************************/
void
mcf5282_sdram_init(void)
{
	int i;

	/*
	 * Check to see if the SDRAM has already been initialized
	 * by a run control tool
	 */
	if (!(MCF5282_SDRAMC_DACR0 & MCF5282_SDRAMC_DACR_RE))
	{
		/* 
		 * Initialize DRAM Control Register: DCR 
		 */
		MCF5282_SDRAMC_DCR = (0
			| MCF5282_SDRAMC_DCR_RTIM_6
			| MCF5282_SDRAMC_DCR_RC((15 * SYSTEM_CLOCK)>>4));

		/* 
		 * Initialize DACR0
		 */
		MCF5282_SDRAMC_DACR0 = (0
			| MCF5282_SDRAMC_DACR_BASE(SDRAM_ADDRESS)
			| MCF5282_SDRAMC_DACR_CASL(1)
			| MCF5282_SDRAMC_DACR_CBM(3)
			| MCF5282_SDRAMC_DACR_PS_32);
			
		/*
		 * Initialize DMR0
		 */
		MCF5282_SDRAMC_DMR0 = (0
			| MCF5282_SDRAMC_DMR_BAM_16M
			| MCF5282_SDRAMC_DMR_V);

		/*	
		 * Set IP (bit 3) in DACR 
		 */
		MCF5282_SDRAMC_DACR0 |= MCF5282_SDRAMC_DACR_IP;

		/* 
		 * Wait 30ns to allow banks to precharge 
		 */
		for (i = 0; i < 5; i++)
		{
			#ifndef __MWERKS__
				asm(" nop");
#else
				asm( nop);
#endif
	}

		/*	
		 * Write to this block to initiate precharge 
		 */
		*(uint32 *)(SDRAM_ADDRESS) = 0xA5A59696;

		/*	
		 * Set RE (bit 15) in DACR 
		 */
		MCF5282_SDRAMC_DACR0 |= MCF5282_SDRAMC_DACR_RE;
			
		/* 
		 * Wait for at least 8 auto refresh cycles to occur 
		 */
		for (i = 0; i < 2000; i++)
		{
			#ifndef __MWERKS__
				asm(" nop");
#else
				asm( nop);
#endif
}

		/*	
		 * Finish the configuration by issuing the IMRS. 
		 */
		MCF5282_SDRAMC_DACR0 |= MCF5282_SDRAMC_DACR_IMRS;
		
		/*
		 * Write to the SDRAM Mode Register 
		 */
		*(uint32 *)(SDRAM_ADDRESS + 0x400) = 0xA5A59696;
	}
}
/********************************************************************/
void
mcf5282_cs_init(void)
{
	/* 
	 * ChipSelect 1 - External SRAM 
	 */
	MCF5282_CS1_CSAR = MCF5282_CS_CSAR_BA(EXT_SRAM_ADDRESS);
	MCF5282_CS1_CSCR = MCF5282_CS_CSCR_AA | MCF5282_CS_CSCR_PS_32;
	MCF5282_CS1_CSMR = MCF5282_CS_CSMR_BAM_512K | MCF5282_CS_CSMR_V;
    
    /* 
	 * ChipSelect 0 - External Flash 
	 */ 
	MCF5282_CS0_CSAR = MCF5282_CS_CSAR_BA(EXT_FLASH_ADDRESS);
	MCF5282_CS0_CSCR = (0
		| MCF5282_CS_CSCR_WS(6)
		| MCF5282_CS_CSCR_AA
		| MCF5282_CS_CSCR_PS_16);
	MCF5282_CS0_CSMR = MCF5282_CS_CSMR_BAM_2M | MCF5282_CS_CSMR_V;
}
/********************************************************************/