?? mcf5282.h
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/*********************************************************************
*
* Copyright:
* 1999-2000 MOTOROLA, INC. All Rights Reserved.
* You are hereby granted a copyright license to use, modify, and
* distribute the SOFTWARE so long as this entire notice is
* retained without alteration in any modified and/or redistributed
* versions, and that such modified versions are clearly identified
* as such. No licenses are granted by implication, estoppel or
* otherwise under any patents or trademarks of Motorola, Inc. This
* software is provided on an "AS IS" basis and without warranty.
*
* To the maximum extent permitted by applicable law, MOTOROLA
* DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
* PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
* SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
* ACCOMPANYING WRITTEN MATERIALS.
*
* To the maximum extent permitted by applicable law, IN NO EVENT
* SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
* INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
* LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
*
* Motorola assumes no responsibility for the maintenance and support
* of this software
********************************************************************/
/*
* File: MCF5282.h
* Purpose: MCF5282 definitions
*
* Notes:
*/
#ifndef _CPU_MCF5282_H
#define _CPU_MCF5282_H
/***********************************************************************/
/*
* Misc. Defines
*/
#ifdef FALSE
#undef FALSE
#endif
#define FALSE (0)
#ifdef TRUE
#undef TRUE
#endif
#define TRUE (1)
#ifdef NULL
#undef NULL
#endif
#define NULL (0)
/***********************************************************************/
/*
* The basic data types
*/
typedef unsigned char uint8; /* 8 bits */
typedef unsigned short int uint16; /* 16 bits */
typedef unsigned long int uint32; /* 32 bits */
typedef signed char int8; /* 8 bits */
typedef signed short int int16; /* 16 bits */
typedef signed long int int32; /* 32 bits */
typedef volatile uint8 vuint8; /* 8 bits */
typedef volatile uint16 vuint16; /* 16 bits */
typedef volatile uint32 vuint32; /* 32 bits */
/***********************************************************************/
/*
* Common M68K & ColdFire definitions
*/
#define ADDRESS uint32
#define INSTRUCTION uint16
#define ILLEGAL 0x4AFC
#define CPU_WORD_SIZE 16
/***********************************************************************/
/*
* Routines and macros for accessing Input/Output devices
*/
#define cpu_iord_8(ADDR) *((volatile uint8 *)(ADDR))
#define cpu_iord_16(ADDR) *((volatile uint16 *)(ADDR))
#define cpu_iord_32(ADDR) *((volatile uint32 *)(ADDR))
#define cpu_iowr_8(ADDR,DATA) *((volatile uint8 *)(ADDR)) = (DATA)
#define cpu_iowr_16(ADDR,DATA) *((volatile uint16 *)(ADDR)) = (DATA)
#define cpu_iowr_32(ADDR,DATA) *((volatile uint32 *)(ADDR)) = (DATA)
/***********************************************************************/
#define MCF5XXX_SR_T (0x8000)
#define MCF5XXX_SR_S (0x2000)
#define MCF5XXX_SR_M (0x1000)
#define MCF5XXX_SR_IPL (0x0700)
#define MCF5XXX_SR_IPL_0 (0x0000)
#define MCF5XXX_SR_IPL_1 (0x0100)
#define MCF5XXX_SR_IPL_2 (0x0200)
#define MCF5XXX_SR_IPL_3 (0x0300)
#define MCF5XXX_SR_IPL_4 (0x0400)
#define MCF5XXX_SR_IPL_5 (0x0500)
#define MCF5XXX_SR_IPL_6 (0x0600)
#define MCF5XXX_SR_IPL_7 (0x0700)
#define MCF5XXX_SR_X (0x0010)
#define MCF5XXX_SR_N (0x0008)
#define MCF5XXX_SR_Z (0x0004)
#define MCF5XXX_SR_V (0x0002)
#define MCF5XXX_SR_C (0x0001)
/***********************************************************************/
/*
* The ColdFire family of processors has a simplified exception stack
* frame that looks like the following:
*
* 3322222222221111 111111
* 1098765432109876 5432109876543210
* 8 +----------------+----------------+
* | Program Counter |
* 4 +----------------+----------------+
* |FS/Fmt/Vector/FS| SR |
* SP --> 0 +----------------+----------------+
*
* The stack self-aligns to a 4-byte boundary at an exception, with
* the FS/Fmt/Vector/FS field indicating the size of the adjustment
* (SP += 0,1,2,3 bytes).
*/
#define MCF5200_RD_SF_FORMAT(PTR) \
((*((uint16 *)(PTR)) >> 12) & 0x00FF)
#define MCF5200_RD_SF_VECTOR(PTR) \
((*((uint16 *)(PTR)) >> 2) & 0x00FF)
#define MCF5200_RD_SF_FS(PTR) \
( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) )
#define MCF5200_SF_SR(PTR) *((uint16 *)(PTR)+1)
#define MCF5200_SF_PC(PTR) *((uint32 *)(PTR)+1)
#if 0
typedef struct
{
uint16 SR;
uint16 FS_FMT_VECTOR_FS;
uint32 PC;
} MCF5200_STACK_FRAME;
#endif
/**********************************************************************
*
* CPU Space Registers
*
***********************************************************************/
/* Bit level definitions and macros */
#define MCF5XXX_CACR_CENB (0x80000000)
#define MCF5XXX_CACR_CPDI (0x10000000)
#define MCF5XXX_CACR_CPD (0x10000000)
#define MCF5XXX_CACR_CFRZ (0x08000000)
#define MCF5XXX_CACR_CINV (0x01000000)
#define MCF5XXX_CACR_DIDI (0x00800000)
#define MCF5XXX_CACR_DISD (0x00400000)
#define MCF5XXX_CACR_INVI (0x00200000)
#define MCF5XXX_CACR_INVD (0x00100000)
#define MCF5XXX_CACR_CEIB (0x00000400)
#define MCF5XXX_CACR_DCM_WR (0x00000000)
#define MCF5XXX_CACR_DCM_CB (0x00000100)
#define MCF5XXX_CACR_DCM_IP (0x00000200)
#define MCF5XXX_CACR_DCM (0x00000200)
#define MCF5XXX_CACR_DCM_II (0x00000300)
#define MCF5XXX_CACR_DBWE (0x00000100)
#define MCF5XXX_CACR_DWP (0x00000020)
#define MCF5XXX_CACR_EUST (0x00000010)
#define MCF5XXX_CACR_CLNF_00 (0x00000000)
#define MCF5XXX_CACR_CLNF_01 (0x00000002)
#define MCF5XXX_CACR_CLNF_10 (0x00000004)
#define MCF5XXX_CACR_CLNF_11 (0x00000006)
#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000)
#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8)
#define MCF5XXX_ACR_EN (0x00008000)
#define MCF5XXX_ACR_SM_USER (0x00000000)
#define MCF5XXX_ACR_SM_SUPER (0x00002000)
#define MCF5XXX_ACR_SM_IGNORE (0x00006000)
#define MCF5XXX_ACR_ENIB (0x00000080)
#define MCF5XXX_ACR_CM (0x00000040)
#define MCF5XXX_ACR_DCM_WR (0x00000000)
#define MCF5XXX_ACR_DCM_CB (0x00000020)
#define MCF5XXX_ACR_DCM_IP (0x00000040)
#define MCF5XXX_ACR_DCM_II (0x00000060)
#define MCF5XXX_ACR_CM (0x00000040)
#define MCF5XXX_ACR_BWE (0x00000020)
#define MCF5XXX_ACR_WP (0x00000004)
#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000)
#define MCF5XXX_RAMBAR_PRI_00 (0x00000000)
#define MCF5XXX_RAMBAR_PRI_01 (0x00004000)
#define MCF5XXX_RAMBAR_PRI_10 (0x00008000)
#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000)
#define MCF5XXX_RAMBAR_WP (0x00000100)
#define MCF5XXX_RAMBAR_CI (0x00000020)
#define MCF5XXX_RAMBAR_SC (0x00000010)
#define MCF5XXX_RAMBAR_SD (0x00000008)
#define MCF5XXX_RAMBAR_UC (0x00000004)
#define MCF5XXX_RAMBAR_UD (0x00000002)
#define MCF5XXX_RAMBAR_V (0x00000001)
/********************************************************************/
/*
* Memory map definitions from linker command files
*/
extern uint8 __IPSBAR[];
/*********************************************************************
*
* System Control Module (SCM)
*
*********************************************************************/
/* Read/Write access macros for general use */
#define MCF5282_SCM_IPSBAR (*(vuint32 *)(void *)(&__IPSBAR[0x0000]))
#define MCF5282_SCM_RAMBAR (*(vuint32 *)(void *)(&__IPSBAR[0x0008]))
#define MCF5282_SCM_CRSR (*(vuint8 *)(void *)(&__IPSBAR[0x0010]))
#define MCF5282_SCM_CWCR (*(vuint8 *)(void *)(&__IPSBAR[0x0011]))
#define MCF5282_SCM_LPICR (*(vuint8 *)(void *)(&__IPSBAR[0x0012]))
#define MCF5282_SCM_CWSR (*(vuint8 *)(void *)(&__IPSBAR[0x0013]))
#define MCF5282_SCM_DMAREQC (*(vuint32 *)(void *)(&__IPSBAR[0x0014]))
#define MCF5282_SCM_MPARK (*(vuint32 *)(void *)(&__IPSBAR[0x001C]))
#define MCF5282_SCM_MPR (*(vuint8 *)(void *)(&__IPSBAR[0x0020]))
#define MCF5282_SCM_PACR0 (*(vuint8 *)(void *)(&__IPSBAR[0x0024]))
#define MCF5282_SCM_PACR1 (*(vuint8 *)(void *)(&__IPSBAR[0x0025]))
#define MCF5282_SCM_PACR2 (*(vuint8 *)(void *)(&__IPSBAR[0x0026]))
#define MCF5282_SCM_PACR3 (*(vuint8 *)(void *)(&__IPSBAR[0x0027]))
#define MCF5282_SCM_PACR4 (*(vuint8 *)(void *)(&__IPSBAR[0x0028]))
#define MCF5282_SCM_PACR5 (*(vuint8 *)(void *)(&__IPSBAR[0x002A]))
#define MCF5282_SCM_PACR6 (*(vuint8 *)(void *)(&__IPSBAR[0x002B]))
#define MCF5282_SCM_PACR7 (*(vuint8 *)(void *)(&__IPSBAR[0x002C]))
#define MCF5282_SCM_PACR8 (*(vuint8 *)(void *)(&__IPSBAR[0x002E]))
#define MCF5282_SCM_GPACR0 (*(vuint8 *)(void *)(&__IPSBAR[0x0030]))
#define MCF5282_SCM_GPACR1 (*(vuint8 *)(void *)(&__IPSBAR[0x0031]))
/* Bit level definitions and macros */
#define MCF5282_SCM_IPSBAR_BA(x) ((x)&0xC0000000)
#define MCF5282_SCM_IPSBAR_V (0x00000001)
#define MCF5282_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
#define MCF5282_SCM_RAMBAR_BDE (0x00000200)
#define MCF5282_SCM_FLASHBAR_BA(x) ((x)&0xFFF80000)
#define MCF5282_SCM_FLASHBAR_BDE (0x00000200)
#define MCF5282_SCM_CRSR_EXT (0x80)
#define MCF5282_SCM_CRSR_CWDR (0x20)
#define MCF5282_SCM_CWCR_CWE (0x80)
#define MCF5282_SCM_CWCR_CWRI (0x40)
#define MCF5282_SCM_CWCR_CWT(x) (((x)&0x07)<<3)
#define MCF5282_SCM_CWCR_CWTA (0x04)
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