?? iis.c
字號(hào):
#include "..\Target\44b.h"
#include "..\Target\44blib.h"
#include "..\Target\def.h"
#include "iis.h"
void _WrL3Addr(U8 data);
void _WrL3Data(U8 data,int halt);
void __irq BDMA0_Done(void);
void __irq BDMA0_Rec_Done(void);
void __irq TR_Done(void);
void __irq RxInt(void);
#define L3D (0x200)//PA9
#define L3M (0x40)//PG6
#define L3C (0x80)//PG7
unsigned char *Buf,*_temp;
volatile unsigned int size=0;
// sword for record
unsigned char *rec_buf;
#define PLAY 0
#define RECORD 1
#define REC_LEN 0xF0000
volatile unsigned int leng,ssize;
volatile char Rec_Done=0;
volatile char mute=1;
unsigned int save_A,save_C,save_E,save_G,save_PC,save_PE,save_PG;
void Record_Iis(void)
{
U32 i;
// ChangePllValue(0x49,0x7,0x1); //MCLK=45.1584MHz <-- 5.6448MHz*8
// Uart_Init(45000000,115200);
// unsigned int save_A,save_C,save_E,save_G,save_PC,save_PE,save_PG;
ChangePllValue(71,5,1); //MCLK=45.1584MHz <-- 5.6448MHz*8
Uart_Init(45200000,115200);
Uart_Printf("[Record test using UDA1341]\n");
save_A=rPCONA;//L3DATA
save_C=rPCONC;//IIS port
save_E=rPCONE;//CODEC clk
save_G=rPCONG;//L3CLK,L3MOD
save_PC=rPUPC;
save_PE=rPUPE;
save_PG=rPUPG;
#if (BUSWIDTH==32)
Uart_Printf("IIS test should be configured 16bit data bus\n");
return;
#else //BUSWIDTH=16
rPCONC |=0xff;//選通iis特性
rPUPC |= 0xf;//禁止上拉電阻
#endif
rPCONE=(rPCONE&0xffff)+(2<<16); //PE:CODECLK
pISR_BDMA0=(unsigned)BDMA0_Rec_Done;
rINTMSK=~(BIT_GLOBAL|BIT_BDMA0);
//for down
rec_buf=(unsigned char *)0xc400000;
// rec_buf=(unsigned short *)0xc400000;
Buf =rec_buf;
for(i=0XC400000;i<(0XC400000+0XF0000);i+=4)
{
*((volatile unsigned *)i)=0x0;
}
Init1341(RECORD);
//for down
rBDISRC0=(1<<30)+(3<<28)+((int)IISFIF); //Half word,fix,IISFIF
//初始DMA源：傳輸數(shù)據(jù)類(lèi)型:半字 加載地址變動(dòng)方向:內(nèi)部接口固定地址 初始源地址
rBDIDES0=(2<<30)+(1<<28)+((int)(rec_buf)); //IO2M,inc,Buf
//初始DMA目標(biāo):內(nèi)部外設(shè)到外部存儲(chǔ)器,加載地址變動(dòng)方向:增量,初始目標(biāo)地址
//for down
rBDICNT0=(1<<30)+(1<<26)+(3<<22)+(1<<21)+(0<<20)+REC_LEN;
//BDMA計(jì)數(shù)寄存器:DMA請(qǐng)求源:IIS,, 中斷模式設(shè)置:當(dāng)終止計(jì)數(shù)時(shí)產(chǎn)生中斷,在DMA計(jì)數(shù)到0時(shí)自動(dòng)加載和自動(dòng)開(kāi)始
rBDICNT0 |= (1<<20);//enable
//使能DMA,必須單獨(dú)設(shè)置
rBDCON0 = 0x0<<2;
/****** IIS Initialize ******/
rIISCON=0x1a; //Rx DMA enable,Rx idle,prescaler enable
//接收DMA請(qǐng)求允許,發(fā)送通道空閑,
rIISMOD=0x49; //Master,Tx,L-ch=low,iis,16bit ch.,codeclk=256fs,lrck=32fs
//0 01 0 0 1 0 01 Master,Tx,L-ch=low,iis,16bit ch.,codeclk=256fs,lrck=32fs
//主模式，接收，左通道低電平,串行數(shù)據(jù)iis格式,每通道串行數(shù)據(jù)位16,主時(shí)鐘頻率256fs,串行時(shí)鐘頻率32fs
rIISPSR=0x33; //Prescaler_A/B enable, value=3
rIISFCON=0x500; //Tx/Rx DMA,Tx/Rx FIFO --> start piling....
Uart_Printf("Press any key to start record!!!\n");
Uart_Getch();
Uart_Printf("Recording...\n");
//--- Rx start
rIISCON |=0x1;
Uart_Printf("Push any key to stop record!!!\n");
while(!Uart_GetKey());
// while(!Rec_Done);
rINTMSK |= BIT_BDMA0;
Rec_Done=0;
//--- IIS Stop
Delay(10); //for end of H/W Rx
rIISCON=0x0; //IIS stop
rBDICNT0=0x0; //BDMA stop
Uart_Printf("End of Record!!!\n");
Uart_Printf("Press any key to play recorded data\n");
Uart_Getch();
size=REC_LEN*2;
Uart_Printf("size=%d\n",size);
Init1341(PLAY);
pISR_BDMA0=(unsigned)BDMA0_Done;
pISR_URXD0=(unsigned)RxInt;
rINTMSK=~(BIT_GLOBAL|BIT_BDMA0);
rBDISRC0=(1<<30)+(1<<28)+((int)(rec_buf));//Buf+0x30));// //Half word,inc,Buf
rBDIDES0=(1<<30)+(3<<28)+((int)IISFIF); //M2IO,fix,IISFIF
rBDICNT0=(1<<30)+(1<<26)+(3<<22)+(1<<21)+(1<<20)+REC_LEN;//size;//
rBDICNT0 |= (1<<20);//enable
//使能DMA,必須單獨(dú)設(shè)置
rBDCON0 = 0x0<<2;
//****** IIS Initialize ******
rIISCON=0x22; //Tx DMA enable,Rx idle,prescaler enable
rIISMOD=0x89; //Master,Tx,L-ch=low,iis,16bit ch.,codeclk=256fs,lrck=32fs
rIISPSR=0x33; //Prescaler_A/B enable, value=3
rIISFCON=0xa00; //Tx/Rx DMA,Tx/Rx FIFO --> start piling....
Uart_Printf("Push any key to exit!!!\n");
//****** IIS Tx Start ******
rIISCON |=0x1;
while(!Uart_GetKey());
//****** IIS Tx Stop ******
rIISCON=0x0; //IIS stop
rBDICNT0=0x0; //BDMA stop
//for down
free(rec_buf);
Cache_Flush();
rNCACHBE0=0x0;
size=0;
rPCONA=save_A;
rPCONC=save_C;
rPCONE=save_E;
rPCONG=save_G;
rPUPC=save_PC;
rPUPE=save_PE;
rPUPG=save_PG;
rINTMSK=BIT_GLOBAL;
ChangePllValue(0x34,0x3,0x1);//Fin=10MHz, Fout=60MHz
Uart_Init(0,115200);
}
void Init1341(char mode)
{
/****** Port Initialize ******/
rPCONA = 0x1ff; //PA9(out):L3D
rPCONG = 0x5000; //PG6:L3M, PG7:L3C
rPUPG |= 0xc0; //disable(pull-up)
rPDATG = L3M|L3C; //L3M=H(start condition)
//L3C=H(start condition)
/****** L3 Interface ******/
_WrL3Addr(0x14+2); //status (000101xx+10)
#ifdef FS441KHZ
_WrL3Data(0x60,0); //0,1(RST),10(SC),000(IF),0(DC)
//STATUS 0: ReSeT,System Clock frequency of 256fs,data Input Format of iis-bus, no DCfilter
#else
_WrL3Data(0x40,0); //0,1,00,000,0
//STATUS 0: ReSeT,System Clock frequency of 256fs,data Input Format of iis-bus, no DCfilter
#endif
_WrL3Addr(0x14+2); //status (000101xx+10)
#ifdef FS441KHZ
_WrL3Data(0x20,0); //0,0,10,000,0 no reset,256fs,no DCfilter,iis
#else
_WrL3Data(0x00,0); //0,0,00,000,0 no reset,512fs,no DCfilter,iis
#endif
_WrL3Addr(0x14+2); //status (000101xx+10)
_WrL3Data(0x81,0);
if(mode)//RECORD
{
_WrL3Addr(0x14+2); //(000101xx+10):STATUS
_WrL3Data(0xa2,0); //1, 0(OGS),1(IGS),0(PAD),0(PDA),0(DS),10(PC)
// Gain of DAC 0 dB,Gain of ADC 6dB,ADC non_inverting,DAC non-inverting
//single speed playback,ADC-on DAC-off
/*//in case of using MIC sensitivity settings
_WrL3Addr(0x14+0); //DATA0 (000101xx+00)
_WrL3Data(0xc4,0); //11000:Extended addr(3 bits),100(addr selected):AG&IG(AG 00 IG1 IG0)
_WrL3Data(0xf0,0); //111(Extended data),1(AGC=1,Enable AGC for MIC Amp.Gain Control)00,00(IG1IG0)
_WrL3Addr(0x14+0); //00:DATA0 (000101xx+00)
_WrL3Data(0xc2,0); ////11000:Extended addr(3 bits),010(addr selected):(MS2,MS1,MS0,MM1,MM0)
_WrL3Data(0xfa,0); //111(Extended data),110(MS=27dB),10(Ch2=on,Ch1=off)
*/
//in case of using Input channel 2 Amp.Gain Control samsung
//first select Input channel 2
_WrL3Addr(0x14+0); //(000101xx+00):DATA0
_WrL3Data(0xc2,0); //11000:Extended addr(3 bits),010(addr selected):(MS2,MS1,MS0,MM1,MM0)
_WrL3Data(0xe2,0); //111(Extended data),000(MS=0dB),10(Ch2=on,Ch1=off)
//then diable AGC and set the IG value
_WrL3Addr(0x14+0); //(000101xx+00):DATA0
_WrL3Data(0xc4,0); //11000:Extended addr(3 bits),100:AG&IG
_WrL3Data(0xe3,0); //111(Extended data),0(AGC=0,disable AGC:manual gain setting through IG(7bits))00,11(IG1 IG0:11)
_WrL3Addr(0x14+0); //DATA0 (000101xx+00)
_WrL3Data(0xc5,0); //11000:Extended addr(3 bits),101:IG6-IG2
_WrL3Data(0xff,0); //111(Extended data),11111:(IG6-IG2:11111)
//The Gain of input channel 2 Amp:Max 60.5dB,Input channel 2 selected
}
//record
//sword ended
}
void _WrL3Addr(U8 data)//通過(guò)L3總線(xiàn)接口寫(xiě)控制數(shù)據(jù)地址(data)到1341芯片
{
U32 vPdata = 0x0; //A端口數(shù)據(jù),L3D=L
U32 vPdatg = 0x0; //G端口數(shù)據(jù)L3M=L(in address mode)/L3C=L
S32 i,j;
rPDATG = vPdatg; //L3M=L
rPDATG |= L3C; //L3C=H
for(j=0;j<4;j++); //tsu(L3) > 190ns;軟件延時(shí)
//PA9:L3D PG6:L3M PG7:L3C
for(i=0;i<8;i++)
{
if(data&0x1)//if data bit is 'H'
{
rPDATG = vPdatg; //L3C=L 形成時(shí)鐘信號(hào)
rPDATA = L3D; //L3D=H
for(j=0;j<4;j++); //tcy(L3) > 500ns軟件延時(shí)
rPDATG = L3C; //L3C=H 與L3C=L結(jié)合形成時(shí)鐘信號(hào)
rPDATA = L3D; //L3D=H
for(j=0;j<4;j++); //tcy(L3) > 500ns
}
else //if data bit is 'L'
{
rPDATG=vPdatg; //L3C=L
rPDATA=vPdata; //L3D=L
for(j=0;j<4;j++); //tcy(L3) > 500ns
rPDATG=L3C; //L3C=H
rPDATA=vPdata; //L3D=L
for(j=0;j<4;j++); //tcy(L3) > 500ns
}
data >>=1;
}
rPDATG=L3C|L3M; //L3M=H,L3C=H
}
void _WrL3Data(U8 data,int halt)//通過(guò)L3總線(xiàn)接口寫(xiě)控制數(shù)據(jù)(data和停止操作)到1341芯片
{
U32 vPdata = 0x0; //L3D=L
U32 vPdatg = 0x0; //L3M/L3C=L
S32 i,j;
if(halt)
{
rPDATG=L3C; //L3C=H(while tstp, L3 interface halt condition)
for(j=0;j<4;j++); //tstp(L3) > 190ns
}
rPDATG=L3C|L3M; //L3M=H(in data transfer mode)
for(j=0;j<4;j++); //tsu(L3)D > 190ns
//PA9:L3DATA PG6:L3MODE PG7:L3CLOCK
for(i=0;i<8;i++)
{
if(data&0x1) //if data bit is 'H'
{
rPDATG=L3M; //L3C=L
rPDATA=L3D; //L3D=H
for(j=0;j<4;j++); //tcy(L3) > 500ns
rPDATG=L3C|L3M; //L3C=H
rPDATA=L3D;//L3D=H
for(j=0;j<4;j++); //tcy(L3) > 500ns
}
else //if data bit is 'L'
{
rPDATG=L3M; //L3C=L
rPDATA=vPdatg; //L3D=L
for(j=0;j<4;j++); //tcy(L3) > 500ns
rPDATG=L3C|L3M; //L3C=H
rPDATA=vPdatg; //L3D=L
for(j=0;j<4;j++); //tcy(L3) > 500ns
}
data>>=1;
}
rPDATG=L3C|L3M; //L3M=H,L3C=H
}
void __irq BDMA0_Done(void)
{
rI_ISPC=BIT_BDMA0; //clear pending bit
WrUTXH0('&');
}
//for record sword
void __irq BDMA0_Rec_Done(void)
{
rI_ISPC=BIT_BDMA0; //clear pending bit
WrUTXH0('#');
}
//sword ended
void __irq RxInt(void)
{
rI_ISPC=BIT_URXD0 ; //clear pending bits
*_temp++=RdURXH0();
}
volatile int Tx_Done;
volatile int Rx_Done;
void Iis_Tx(void)
{
unsigned int i, save_conC, save_pupC;
unsigned short *txdata;
Tx_Done=0;
Uart_TxEmpty(0);
ChangePllValue(0x69,0x17,0x0); //10MHz --> MCLK=45.1584MHz <-- 5.6448MHz*8
Uart_Init(45200000,115200);
Uart_Printf("[IIS Slave Tx test]\n");
save_conC=rPCONC;
save_pupC=rPUPC;
rPCONC |=0xff;//IIS port
rPUPC |= 0xf;
pISR_BDMA0=(unsigned)TR_Done;
rINTMSK=~(BIT_GLOBAL|BIT_BDMA0);
/****** Tx DATA initialize ******/
txdata=(unsigned short *)malloc(0x10000);
for(i=0;i<0x10000;i++)
*(txdata+i)=i;
rNCACHBE0= ((int)txdata>>12) + ( (((int)txdata>>12) +0x20)<<16 );//non-cachable 65KB*2
/****** BDMA0 Initialize ******/
rBDISRC0=(1<<30)+(1<<28)+(int)(txdata); //Half word,inc,Buf
rBDIDES0=(1<<30)+(3<<28)+((int)IISFIF); //M2IO,fix,IISFIF
rBDICNT0=(1<<30)+(1<<26)+(3<<22)+(0<<21)+(0<<20)+0x10000*2;
rBDICNT0 |= (1<<20);//enable
//iis,reserved,end_int,1_tx,DMA enable,COUNT
rBDCON0 = 0x0<<2;
/****** IIS Initialize ******/
rIISCON=0x22; //Tx DMA enable,Rx idle,prescaler enable
rIISMOD=0x189; //Master,Tx,L-ch=low,iis,16bit ch.,codeclk=256fs,lrck=32fs
rIISPSR=0x33; //Prescaler_A/B enable, value=3
rIISFCON=0xa00; //Tx/Rx DMA,Tx/Rx FIFO --> start piling....
/****** Tx start ******/
rIISCON |=0x1;
while(!Tx_Done);
/****** Tx Stop(Slave) ******/
Delay(10);
rIISCON=0x0; //IIS stop
rIISFCON=0x0; //for FIFO flush
rBDICNT0=0x0; //BDMA stop
Uart_Printf("\nTx End...\n");
Uart_Printf("Last 256bytes in 65KB transferred data\n");
for(i=0;i<0x100;i++)
Uart_Printf("%04x,",*(txdata+0xff00+i));
free(txdata);
Cache_Flush();
rNCACHBE0=0x0;
rPCONC=save_conC;
rPUPC=save_pupC;
rINTMSK=BIT_GLOBAL;
ChangePllValue(0x34,0x3,0x1);//Fin=10MHz, Fout=60MHz
Uart_Init(0,115200);
}
void __irq TR_Done(void)
{
rI_ISPC=BIT_BDMA0; //clear pending bit
Rx_Done=1;
Tx_Done=1;
//WrUTXH0('.');
}
void Iis_Rx(void)
{
unsigned int i, j, save_conC,save_pupC;
unsigned short *rxdata;
Rx_Done=0;
Uart_TxEmpty(0);
ChangePllValue(0x69,0x17,0x0); //10MHz --> MCLK=45.1584MHz <-- 5.6448MHz*8
Uart_Init(45200000,115200);
Uart_Printf("[IIS Master Rx test]\n");
save_conC=rPCONC;
save_pupC=rPUPC;
rPCONC |=0xff;//IIS port
rPUPC |= 0xf;
pISR_BDMA0=(unsigned)TR_Done;
rINTMSK=~(BIT_GLOBAL|BIT_BDMA0);
/****** Rx Buf initialize ******/
rxdata=(unsigned short *)malloc(0x10000);
//Uart_Printf("Receive addr=0x%x\n",rxdata);
for(i=0;i<0x10000;i++)
*(rxdata+i)=0;
rNCACHBE0= ((int)rxdata>>12) + ( (((int)rxdata>>12) +0x20)<<16 );//non-cachable 65KB*2
/****** BDMA0 Initialize ******/
rBDISRC0=(1<<30)+(3<<28)+((int)IISFIF); //Half word,fix,IISFIF
rBDIDES0=(2<<30)+(1<<28)+(int)(rxdata); //IO2M,increment,rxdata
rBDICNT0=(1<<30)+(1<<26)+(3<<22)+(0<<21)+(0<<20)+0x10000*2;
//iis,reserved,end_int,1_tx,DMA disable,COUNT
rBDICNT0 |= (1<<20);//enable
rBDCON0 = 0x0<<2;
/****** IIS Initialize ******/
rIISCON=0x12; //Rx DMA enable,Tx idle,prescaler enable
rIISMOD=0x049; //Slave,Tx,L-ch=low,iis,16bit ch.,codeclk=256fs,lrck=32fs
rIISPSR=0x33; //Prescaler_A/B enable, value=3
rIISFCON=0x500; //Tx/Rx DMA,Tx/Rx FIFO --> start piling....
/****** Rx start ******/
rIISCON |=0x1;
while(!Rx_Done);
/****** Rx Stop(Master) ******/
rIISCON=0x0; //IIS stop
rIISFCON=0x0; //for FIFO flush
rBDICNT0=0x0; //BDMA stop
/****** Check Rx data ******/
for(i=0;i<0x10000;i++)
{
j=*(rxdata+i);
if(j!=i)
{
Uart_Printf("IIS Rx fail!(Rx=%04x, Tx=%04x)\n", j,i);
break;
}
}
if(j+1==i)
Uart_Printf("\nIIS Rx O.K.!!!\n");
Uart_Printf("Last 256bytes in 65KB received data\n");
for(i=0;i<0x100;i++)
Uart_Printf("%04x,",*(rxdata+0xff00+i));
free(rxdata);
Cache_Flush();
rNCACHBE0=0x0;
rPCONC=save_conC;
rPUPC=save_pupC;
rINTMSK=BIT_GLOBAL;
ChangePllValue(0x34,0x3,0x1);//Fin=10MHz, Fout=60MHz
Uart_Init(0,115200);
}
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