;**************************************************************
;Copyright(C), 2006-2007, Allwinner Microelectronic Co., Ltd.
;File Name： serial.s
;Author： Wang Yugang
;Version  1.0
;Date  2007.7.27
;Description： test void UART_printf( const char * str, ...)
;**************************************************************
		
		get  HD_REG.s
		import test_UART_printf
		import UART_putchar
		import UART_puts
		import UART_getchar
		import UART_getchar_with_display
		import serial_term
		import test_lcd
		
		export jump_to
		export light1
		export light2
		export light3
		export light4
		

		
		area  init, code, readonly
		code32

		
		entry

start


;******************************************************************

; disable watch dog timer
	mov	r1, #WTCON
	mov	r2, #0x0
	str	r2, [r1]


;disable all interrupts
	mrs r0, cpsr
	bic  r0, r0, #MODE_MASK
	orr  r0, r0, #SVC_MODE
	orr  r0, r0, #F_BIT
	orr  r0, r0, #I_BIT
	msr cpsr_c, r0
	
	mov	r1, #INT_CTL_BASE
	mov	r2, #0xffffffff
	str	r2, [r1, #oINTMSK]
	ldr	r2, =0x7ff
	str	r2, [r1, #oINTSUBMSK]	


;initialise system clocks
	mov	r1, #CLK_CTL_BASE
	mvn	r2, #0xff000000
	str	r2, [r1, #oLOCKTIME]
	
	mov	r1, #CLK_CTL_BASE
	ldr	r2, =0x5
	str	r2, [r1, #oCLKDIVN]

	mrc	p15, 0, r1, c1, c0, 0		; read ctrl register 
	orr	r1, r1, #0xc0000000		    ; Asynchronous  
	mcr	p15, 0, r1, c1, c0, 0		; write ctrl register

	mov	r1, #CLK_CTL_BASE
	ldr 	r2, =0x7f021			; clock user set
	str	r2, [r1, #oMPLLCON]






; initialise SDRAM
	mov	r1, #MEM_CTL_BASE
	adrl	r2, mem_cfg_val
	add	r3, r1, #52
1	ldr	r4, [r2], #4
	str	r4, [r1], #4
	cmp	r1, r3
	bne	%1




;initialise LED
	mov	r1, #GPIO_CTL_BASE
	add	r1, r1, #oGPIO_B
	ldr	r2, =0x55555
	str	r2, [r1, #oGPIO_CON]
	ldr	r2, =0xfff
	str	r2, [r1, #oGPIO_UP]		




	bl  light2
	
	
	


; set GPIO for UART
	mov	r1, #GPIO_CTL_BASE
	add	r1, r1, #oGPIO_H
	ldr	r2, =vGPHCON	
	str	r2, [r1, #oGPIO_CON]
	ldr	r2, =vGPHUP
	str	r2, [r1, #oGPIO_UP]	
	bl	InitUART
	

;
;	Import some important variables for later use
;

    IMPORT |Image$$RO$$Base|    
	IMPORT |Image$$RO$$Limit|   
	IMPORT |Image$$RW$$Base|   
	IMPORT |Image$$RW$$Limit| 	
	IMPORT |Image$$ZI$$Base| 	
	IMPORT |Image$$ZI$$Limit| 


;
; Copy RW & ZI to SDRAM
;
	LDR r0, =|Image$$RO$$Limit| 	
	LDR r1, =|Image$$RW$$Base| 		
	LDR r3, =|Image$$ZI$$Base| 		

	CMP r0, r1 
	BEQ %1
 
0 	CMP r1, r3 						; Copy init data
	LDRCC r2, [r0], #4
	STRCC r2, [r1], #4
	BCC %0

1 	LDR r1, =|Image$$ZI$$Limit| 	; Top of zero init segment
	MOV r2, #0

2 	CMP r3, r1 						; Zero init
	STRCC r2, [r3], #4
	BCC %2






	ldr sp, =TEMP_STACK_TOP                               ;.......................................
	mov fp, #0
	bl  test_UART_printf
	
	
		
	ldr r0, =choice_start
	bl  UART_puts
	bl  PrintNewline
	
	ldr r0, =choice_1
	bl  UART_puts
	bl  PrintNewline
	
	ldr r0, =choice_2
	bl  UART_puts
	bl  PrintNewline
	
	ldr r0, =choice_3
	bl  UART_puts
	bl  PrintNewline
	
	bl  light3
	

	
	
	
	
getinput
	ldr r1, =UART_CTL_BASE
	bl  UART_getchar_with_display
	
	mov r6, r0
	cmp r6, #'1'
	bne next1
	ldr r0, =answer_1
	bl  UART_puts
	bl  PrintNewline
	b goon
next1
	cmp r6, #'2'
	bne next2
	ldr r0, =answer_2
	bl  UART_puts
	bl  PrintNewline
	b goon
next2
	cmp r6, #'3'
	bne next3
	ldr r0, =answer_3
	bl  UART_puts
	bl  PrintNewline
	b goon
next3
	ldr r0, =ERROR
	bl  UART_puts
	bl  PrintNewline
	b   getinput
	

goon





	bl  test_lcd                                  ;..........................
	                                                 ;...........................
	
	
	
	
	
;let LED4,LED3,LED2,LED1 on in turn 
	mov	r1, #GPIO_CTL_BASE
	add	r1, r1, #oGPIO_B	
	ldr r5, =0x77777777	
rotate
	
	mov r3, #0x000a0000
delay                                  ;delay a while
	subs r3, r3, #1
	bne delay
	
	str	r5, [r1, #oGPIO_DAT]
	mov r5,r5,ror #1
	
	b   rotate



	



loop  
	b  loop                            ; ifinite loop
	
	
	
	
	
	
	
;
; subroutines
;


; Initialize UART
;
; r0 = number of UART port
InitUART
	ldr	r1, =UART_CTL_BASE
	ldr	r2, =vUFCON
	str	r2, [r1, #oUFCON]         
	ldr r2, =vUMCON
	str	r2, [r1, #oUMCON]         
	ldr r2, =vULCON
	str	r2, [r1, #oULCON]         
	ldr	r2, =vUCON
	str	r2, [r1, #oUCON]          

	mov	r2, #UART_BRD              ;UART_BRD = ((UART_PCLK  / (UART_BAUD_RATE * 16)) - 1)
	str	r2, [r1, #oUBRDIV]

	mov	r3, #100
	mov	r2, #0x0
2	sub	r3, r3, #0x1
	tst	r2, r3
	bne	%2


	mov	pc, lr
	
	
	



PrintNewline
	mov r4, lr
	
	mov	r0, #'\r'
	bl	UART_putchar
	mov	r0, #'\n'
	bl	UART_putchar
	
	mov pc, r4
	
	
	
	
	




	
	


light1
	mov r5, #0x00000dd0
	mov	r1, #GPIO_CTL_BASE
	add	r1, r1, #oGPIO_B
	str	r5, [r1, #oGPIO_DAT]
	mov pc, lr

light2
	mov r5, #0x00000bb0
	mov	r1, #GPIO_CTL_BASE
	add	r1, r1, #oGPIO_B
	str	r5, [r1, #oGPIO_DAT]
	mov pc, lr
	
light3
	mov r5, #0x00000770
	mov	r1, #GPIO_CTL_BASE
	add	r1, r1, #oGPIO_B
	str	r5, [r1, #oGPIO_DAT]
	mov pc, lr
	
light4
	mov r5, #0x00000ee0
	mov	r1, #GPIO_CTL_BASE
	add	r1, r1, #oGPIO_B
	str	r5, [r1, #oGPIO_DAT]
	mov pc, lr
	
	
		
	


;
; jump_to: jump to somewhere and execute.
;r0: intput, contains address .
;
jump_to
	mov pc, r0
	mov pc, lr
	
	
;
; DATA SETTION
;
	align 4
HEX_TO_ASCII_TABLE 
	DCB	"0123456789ABCDEF"
STR_STACK 
	DCB	"xTKP"
STR_UNDEF 
	DCB	"UNDF"
STR_SWI 
	DCB	"xWI "
STR_PREFETCH_ABORT 
	DCB	"PABT"
STR_DATA_ABORT 
	DCB	"DABT"
STR_IRQ 
	DCB	"IRQ "
STR_FIQ 
	DCB	"FIQ"
STR_NOT_USED 
	DCB	"NUxD"
	align 2
STR_OK 
	DCB	"OK  "
STR_FAIL 
	DCB	"FAIL"
STR_CR 
	DCB  "\r\n"
	
	align 1
choice_start
	DCB "\nYou have following choices:",0
choice_1
	DCB "1.we can tell you who is the best man in the world.",0
choice_2
	DCB "2.we can tell you who is your boss.",0
choice_3
	DCB "3.we can tell you whether you will be able to become a multimillionaire.",0
answer_1
	DCB "\nYour input is 1. The best man in the world is Wang Yugang.",0
answer_2
	DCB "\nYour input is 2. Your boss is Zhang Gongji.",0		
answer_3
	DCB "\nYour input is 3. You MUST become a multimillionaire soon.",0
ERROR
	DCB "\nYour input is invalid. Please input again.",0	
	
	
	
	ALIGN 4
mem_cfg_val
	DCD	vBWSCON
	DCD	vBANKCON0
	DCD	vBANKCON1
	DCD	vBANKCON2
	DCD	vBANKCON3
	DCD	vBANKCON4
	DCD	vBANKCON5
	DCD	vBANKCON6
	DCD	vBANKCON7
	DCD	vREFRESH
	DCD	vBANKSIZE
	DCD	vMRSRB6
	DCD	vMRSRB7
	
	
	
	end