//******************************************************************************
//  ANX Company SRC 
//  Ver 1.51
//  2006/05/11
//******************************************************************************
//******************************************************************************
//  2006/06/06
//  define AFIFO_CTRL_REG 0xB4
//  updated by xiaoyong
//******************************************************************************



#ifndef anx9021_h
#define anx9021_h

#include <stdio.h>
#include <stdarg.h>
#include "i2c_intf.h"
#include "Timer.h"
#include "mcu.h"
#include "Uart_int.h"

typedef unsigned int WORD;
typedef unsigned char BYTE;
typedef bit BOOL;

#define ANX9021_FW_VER 1.56
#define INPUT_PORT bit 

#define DVI_MODE 0x00
#define HDMI_MODE 0x01
#define INPUT_HDMI 1
#define INPUT_HDMI2 0
#define KILL_BOOST 0

#define ANX9021_ON 1
#define ANX9021_OFF 0

extern bit enable_debug_output;
extern bit restart_system;


void ANX9021_PowerCtrl_API(BYTE onoff);
void ANX9021_HPD_Port0(int delaytime);
void ANX9021_HPD_Port1(int delaytime);
    
BYTE ANX9021_ReadI2C_RX0(BYTE sub_addr, BYTE *rxdata);
BYTE ANX9021_WriteI2C_RX0(BYTE sub_addr, BYTE txdata);
BYTE ANX9021_ReadI2C_RX1(BYTE sub_addr,  BYTE *rxdata);
BYTE ANX9021_WriteI2C_RX1(BYTE sub_addr,  BYTE txdata);
void ANX9021_Chip_Located(void);
// INPUT_PORT is a indicator to judge which port is used
void ANX9021_HDMI_Port_Switch(INPUT_PORT B_InputConnector);
void ANX9021_Int_Process(void);
void ANX9021_Timer_Process(void);

//Use for digital video output fomat   
#define RGB444 0x00
#define RGB444_CLK48B 0x01
#define YCbCr444 0x80
#define YCbCr444_CLK48B 0x81
#define YCbCr422 0xC0
#define YCbCr422_656 0xD0
#define YCbCr422_YCMUX 0xE0
#define YCbCr422_656_YCMUX 0xF0



//**************** User defines of chip configuration******************//

// Analog video ouput enable
#define ANALOG_VID_EN 0x01      //0x00  Disable analog video output
                                //0x01  Enable analog video output

#define VIDEO_OUTPUT_FORMAT RGB444

#define MCLK_SEL      0x00     //0x00 Use ANX9021 MCLK output
                               //0x01 Use external MCLK (MCLK input: Pin 87)

#define MCLK_FREQ_SEL 0x00     // 0x00 Fmclk = 128*Fs
                               // 0x10 Fmclk = 256*Fs
                               // 0x20 Fmclk = 384*Fs
                               // 0x30 Fmclk = 512*Fs

#define AUD_I2S_EN    0x01     //0x00 Disable I2S audio output
                               //0x01 Enable I2S audio output   
                               
#define AUD_SPDIF_EN  0x00     //0x00 Disable SPDIF audio output
                               //0x01 Enable SPDIF audio output   


//**************** End of User Defines ********************************//



//Use For ANX STATE Machine //
#define MONITOR_CKDT 0x01
#define WAIT_SCDT 0x02
#define WAIT_VIDEO 0x03
#define WAIT_AUDIO 0x04
#define PLAYBACK 0x05



// Threshhold Time //
#define VIDEO_STABLE_TH 3     
#define AUDIO_STABLE_TH 1
#define SCDT_EXPIRE_TH 10
#define SCDT_EXPIRE_TH_1 5
#define AFIFO_OV_TH 4
#define AUTH_START_TH 1
#define AUTH_TIMER_TH 20
#define ANX9021_FIFO_TH 50   
#define ANX9021_POP_NOISE_CNT 5
#define ANX9021_POP_NOISE_TH 2

// Application Define Value //
#define ANX9021_INTR_STATE_REG_ON_Check 0x01
#define ANX9021_SCDT_CHANGE 0x08
#define ANX9021_HDMI_DVI_MODE_CHANGE 0x80
#define ANX9021_NEW_AVI_DECT 0x01
#define ANX9021_CTS_ACR_CHANGE 0xF0
#define ANX9021_CTS_RECV 0x04 
#define ANX9021_AUDIO_RECV 0x02
#define ANX9021_HDCP_ERROR 0x40
#define ANX9021_AAC_MUTE 0x40
#define ANX9021_SYNC_DECT 0x01
#define ANX9021_AV_MUTE_STAT 0x04
#define ANX9021_HDMI_MODE 0x10
#define ANX9021_AUD_MUTE 0x02
#define ANX9021_VID_MUTE 0x01
#define ANX9021_TMDS_Power_DOWN 0xF7 
#define ANX9021_TMDS_Power_ON 0xFF
#define ANX9021_ID_RX0 0x60
#define ANX9021_ID_RX1 0x68



// Registers in address 0x60 
#define VND_IDL_REG 0x00
#define VND_IDH_REG 0x01
#define DEV_IDL_REG 0x02
#define DEV_IDH_REG 0x03
#define DEV_REV_REG 0x04
#define SRST_REG 0x05
#define STATE_REG 0x06
#define SYS_CTRL1_REG 0x08
#define PORT_SEL_REG 0x09
#define HDCP_BKSV1_REG 0x1A
#define HDCP_BKSV2_REG 0x1B
#define HDCP_BKSV3_REG 0x1C
#define HDCP_BKSV4_REG 0x1D
#define HDCP_BKSV5_REG 0x1E
#define HDCP_RI1_REG 0x1F
#define HDCP_RI2_REG 0x20
#define HDCP_PJ_REG 0x17
#define HDCP_AKSV1_REG 0x21
#define HDCP_AKSV2_REG 0x22
#define HDCP_AKSV3_REG 0x23
#define HDCP_AKSV4_REG 0x24
#define HDCP_AKSV5_REG 0x25
#define HDCP_AINFO_REG 0x18
#define HDCP_AN1_REG 0x26
#define HDCP_AN2_REG 0x27
#define HDCP_AN3_REG 0x28
#define HDCP_AN4_REG 0x29
#define HDCP_AN5_REG 0x2A
#define HDCP_AN6_REG 0x2B
#define HDCP_AN7_REG 0x2C
#define HDCP_AN8_REG 0x2D
#define BCAPS_SET_REG 0x2E
#define SHD_BSTAT1_REG 0x2F
#define SHD_BSTAT2_REG 0x30
#define HDCPDEBUG_REG 0x31
#define HDCP_STAT_REG 0x32
#define HDCP_DEVID_REG 0x19
#define H_RESL_REG 0x3A
#define H_RESH_REG 0x3B
#define V_RESL_REG 0x3C
#define V_RESH_REG 0x3D
#define DE_PIXL_REG 0x4E
#define DE_PIXH_REG 0x4F
#define DE_LINL_REG 0x50
#define DE_LINH_REG 0x51
#define VID_VTAVL_REG 0x52
#define VID_VFP_REG 0x53
#define VID_STAT_REG 0x55
#define VID_HFP_REG 0x59
#define VID_HSWIDL_REG 0x5B
#define VID_HSWIDH_REG 0x5C
#define VID_MODE_REG 0x4A
#define VID_MODE2_REG 0x49
#define VID_CTRL_REG 0x48
#define VID_F2BPM_REG 0x54
#define VID_CHLCL_REG 0x57
#define VID_CHLCH_REG 0x58
#define VID_PREPC_REG 0x5A
#define VID_SERPC_REG 0x5D
#define VID_POSTPC_REG 0x5E
#define VID_BLANK1_REG 0x4B
#define VID_BLANK2_REG 0x4C
#define VID_BLANK3_REG 0x4D
#define VID_CH_MAP_REG 0x56
#define VID_AOF_REG 0x5F
#define VID_XPCNT_REG 0x6F
#define INTR_STATE_REG 0x70
#define INTR1_MASK_REG 0x75
#define INTR2_MASK_REG 0x76
#define INTR3_MASK_REG 0x77
#define INTR4_MASK_REG 0x78
#define INTR5_MASK_REG 0x7D
#define INTR6_MASK_REG 0x7E
#define INT_CTRL_REG 0x79
#define INTR1_REG 0x71
#define INTR2_REG 0x72
#define INTR3_REG 0x73
#define INTR4_REG 0x74
#define IP_CTRL_REG 0x7A
#define INTR5_REG 0x7B
#define INTR6_REG 0x7C
#define EPST_REG 0xF9
#define EPCM_REG 0xFA
#define AEC_CTRL_REG 0xB5
#define ECC_CTRL_REG 0xBB
#define ECCERR_CNT_REG 0xBC
#define AEC_EN0_REG 0xB6
#define AEC_EN1_REG 0xB7
#define AEC_EN2_REG 0xB8

#define TMDS_PRT0_EQ_REG 0xA4
#define TMDS_PRT1_EQ_REG 0xA5
#define TMDS_EQ2_REG 0xA6
#define TMDS_EQ_VCOM_REG 0xA7
#define TMDS_RXTERM_REG 0xA8
#define TMDS_PLL_CTRL1_REG 0xA9
#define TMDS_PLL_CTRL2_REG 0xAA
#define TMDS_DLL1_CTRL_REG 0xAB
#define TMDS_DLL2_CTRL2_REG 0xAC
#define TMDS_TEST_CTRL_REG 0xAD
#define TMDS_DEBUG_REG 0xAE
#define TMDS_PLL_RNG_CTRL_REG 0xAF
#define TMDS_PLL_RNG_STATUS_REG 0xB0
#define TMDS_PLL_CLK_STATUS_REG 0xB1
#define AFIFO_CTRL_REG 0xB4

#define SRST2_REG 0x95
#define TMDS_CH0_SYNC_STAT_REG 0x96
#define TMDS_CH1_SYNC_STAT_REG 0x97
#define TMDS_CH2_SYNC_STAT_REG 0x98
#define TMDS_CH_ALIGN_STAT_REG 0x99
#define VID_CTRL2_REG 0x9A
#define EEPROM_PROTECT1_REG 0x9B
#define EEPROM_PROTECT2_REG 0x9C
#define EEPROM_PROTECT3_REG 0x9D
#define EEPROM_CFG_REG 0x9E
#define EEPROM_RW_REG_REG 0x9F
#define EEPROM_READ_DATA_REG 0xA0
#define EEPROM_WRITE_DATA_REG 0xA1
#define DAC_CFG1_REG 0xA2
#define DAC_CFG2_REG 0xA3

#define TMDS_PRBS_CTL_REG 0xB2
#define SOFTMUTE_CTRL_REG 0xB9
#define CHIP_CTRL_REG 0xB3
#define PACKET_CTRL_REG 0xBA

// Registers in address 0x68 //
#define ACR_CTRL1_REG 0x00
#define ACR_CTRL2_REG 0x01
#define FREQ_SVAL_REG 0x02
#define N_SVAL1_REG 0x03
#define N_SVAL2_REG 0x04
#define N_SVAL3_REG 0x05
#define N_HVAL1_REG 0x06
#define N_HVAL2_REG 0x07
#define N_HVAL3_REG 0x08
#define CTS_SVAL1_REG 0x09
#define CTS_SVAL2_REG 0x0A
#define CTS_SVAL3_REG 0x0B
#define CTS_HVAL1_REG 0x0C
#define CTS_HVAL2_REG 0x0D
#define CTS_HVAL3_REG 0x0E
#define ACR_INT_N_REG 0x10
#define ACR_FRAC_N1_REG 0x11
#define ACR_FRAC_N2_REG 0x12
#define ACR_FRAC_N3_REG 0x13
#define ACR_PLL_DEBUG1_REG 0x14
#define ACR_PLL_DEBUG2_REG 0x15
#define ACR_CTRL3_REG 0x16
#define PCLK_FS_REG 0x17

#define I2S_CTRL1_REG 0x26
#define I2S_CTRL2_REG 0x27
#define I2S_MAP_REG 0x28
#define AUD_CTRL_REG 0x29
#define CHST1_REG 0x2A
#define CHST2_REG 0x2B
#define CHST3_REG 0x2C
#define SW_OW_REG 0x2E
#define OW_CHST2_REG 0x2F
#define CHST4_REG 0x30
#define CHST5_REG 0x31
#define AUDO_MUTE_REG 0x32
#define HDMI_STAT_REG 0x34
#define HDMI_CRIT1_REG 0x35
#define HDMI_MUTE_REG 0x37
#define HDMI_CRIT2_REG 0x38
#define PD_TOT_REG 0x3C
#define PD_SYS2_REG 0x3E
#define PD_SYS_REG 0x3F
#define AVI_VID_REG 0x47
#define MPEG_DEC_REG 0xBF
#define SPD_DEC_REG 0x7F
#define ACP_DEC_REG 0xFF


#endif