#define GPIO73_MBGNT_MD		(73 | GPIO_ALT_FN_1_OUT)#define GPIO74_LCD_FCLK_MD	(74 | GPIO_ALT_FN_2_OUT)#define GPIO75_LCD_LCLK_MD	(75 | GPIO_ALT_FN_2_OUT)#define GPIO76_LCD_PCLK_MD	(76 | GPIO_ALT_FN_2_OUT)#define GPIO77_LCD_ACBIAS_MD	(77 | GPIO_ALT_FN_2_OUT)#define GPIO78_nCS_2_MD		(78 | GPIO_ALT_FN_2_OUT)#define GPIO79_nCS_3_MD		(79 | GPIO_ALT_FN_2_OUT)#define GPIO80_nCS_4_MD		(80 | GPIO_ALT_FN_2_OUT)/* * Power Manager */#define PMCR		__REG(0x40F00000)  /* Power Manager Control Register */#define PSSR		__REG(0x40F00004)  /* Power Manager Sleep Status Register */#define PSPR		__REG(0x40F00008)  /* Power Manager Scratch Pad Register */#define PWER		__REG(0x40F0000C)  /* Power Manager Wake-up Enable Register */#define PRER		__REG(0x40F00010)  /* Power Manager GPIO Rising-Edge Detect Enable Register */#define PFER		__REG(0x40F00014)  /* Power Manager GPIO Falling-Edge Detect Enable Register */#define PEDR		__REG(0x40F00018)  /* Power Manager GPIO Edge Detect Status Register */#define PCFR		__REG(0x40F0001C)  /* Power Manager General Configuration Register */#define PGSR0		__REG(0x40F00020)  /* Power Manager GPIO Sleep State Register for GP[31-0] */#define PGSR1		__REG(0x40F00024)  /* Power Manager GPIO Sleep State Register for GP[63-32] */#define PGSR2		__REG(0x40F00028)  /* Power Manager GPIO Sleep State Register for GP[84-64] */#define RCSR		__REG(0x40F00030)  /* Reset Controller Status Register */#define PSSR_RDH	(1 << 5)	/* Read Disable Hold */#define PSSR_PH		(1 << 4)	/* Peripheral Control Hold */#define PSSR_VFS	(1 << 2)	/* VDD Fault Status */#define PSSR_BFS	(1 << 1)	/* Battery Fault Status */#define PSSR_SSS	(1 << 0)	/* Software Sleep Status */#define PCFR_DS		(1 << 3)	/* Deep Sleep Mode */#define PCFR_FS		(1 << 2)	/* Float Static Chip Selects */#define PCFR_FP		(1 << 1)	/* Float PCMCIA controls */#define PCFR_OPDE	(1 << 0)	/* 3.6864 MHz oscillator power-down enable */#define RCSR_GPR	(1 << 3)	/* GPIO Reset */#define RCSR_SMR	(1 << 2)	/* Sleep Mode */#define RCSR_WDR	(1 << 1)	/* Watchdog Reset */#define RCSR_HWR	(1 << 0)	/* Hardware Reset *//* * SSP Serial Port Registers */#define SSCR0		__REG(0x41000000)  /* SSP Control Register 0 */#define SSCR1		__REG(0x41000004)  /* SSP Control Register 1 */#define SSSR		__REG(0x41000008)  /* SSP Status Register */#define SSITR		__REG(0x4100000C)  /* SSP Interrupt Test Register */#define SSDR		__REG(0x41000010)  /* (Write / Read) SSP Data Write Register/SSP Data Read Register *//* * MultiMediaCard (MMC) controller */#define MMC_STRPCL	__REG(0x41100000)  /* Control to start and stop MMC clock */#define MMC_STAT	__REG(0x41100004)  /* MMC Status Register (read only) */#define MMC_CLKRT	__REG(0x41100008)  /* MMC clock rate */#define MMC_SPI		__REG(0x4110000c)  /* SPI mode control bits */#define MMC_CMDAT	__REG(0x41100010)  /* Command/response/data sequence control */#define MMC_RESTO	__REG(0x41100014)  /* Expected response time out */#define MMC_RDTO	__REG(0x41100018)  /* Expected data read time out */#define MMC_BLKLEN	__REG(0x4110001c)  /* Block length of data transaction */#define MMC_NOB		__REG(0x41100020)  /* Number of blocks, for block mode */#define MMC_PRTBUF	__REG(0x41100024)  /* Partial MMC_TXFIFO FIFO written */#define MMC_I_MASK	__REG(0x41100028)  /* Interrupt Mask */#define MMC_I_REG	__REG(0x4110002c)  /* Interrupt Register (read only) */#define MMC_CMD		__REG(0x41100030)  /* Index of current command */#define MMC_ARGH	__REG(0x41100034)  /* MSW part of the current command argument */#define MMC_ARGL	__REG(0x41100038)  /* LSW part of the current command argument */#define MMC_RES		__REG(0x4110003c)  /* Response FIFO (read only) */#define MMC_RXFIFO	__REG(0x41100040)  /* Receive FIFO (read only) */#define MMC_TXFIFO	__REG(0x41100044)  /* Transmit FIFO (write only) *//* * Core Clock */#define CCCR		__REG(0x41300000)  /* Core Clock Configuration Register */#define CKEN		__REG(0x41300004)  /* Clock Enable Register */#define OSCC		__REG(0x41300008)  /* Oscillator Configuration Register */#define CCSR		__REG(0x4130000C)  /* Core Clock Status Register */#define CCCR_A		(1 << 25)	/* A bit */#define CCCR_N_MASK	0x0380		/* Run Mode Frequency to Turbo Mode Frequency Multiplier */#define CCCR_M_MASK	0x0060		/* Memory Frequency to Run Mode Frequency Multiplier */#define CCCR_L_MASK	0x001f		/* Crystal Frequency to Memory Frequency Multiplier */#define CLKCFG_T    	(1 << 0)      	/* Turbo mode */#define CLKCFG_F     	(1 << 1)	/* Frequnce change */#define CLKCFG_B     	(1 << 3)	/* Fast-bus mode */#define CKEN16_LCD	(1 << 16)	/* LCD Unit Clock Enable */#define CKEN14_I2C	(1 << 14)	/* I2C Unit Clock Enable */#define CKEN13_FICP	(1 << 13)	/* FICP Unit Clock Enable */#define CKEN12_MMC	(1 << 12)	/* MMC Unit Clock Enable */#define CKEN11_USB	(1 << 11)	/* USB Unit Clock Enable */#define CKEN8_I2S	(1 << 8)	/* I2S Unit Clock Enable */#define CKEN7_BTUART	(1 << 7)	/* BTUART Unit Clock Enable */#define CKEN6_FFUART	(1 << 6)	/* FFUART Unit Clock Enable */#define CKEN5_STUART	(1 << 5)	/* STUART Unit Clock Enable */#define CKEN3_SSP	(1 << 3)	/* SSP Unit Clock Enable */#define CKEN2_AC97	(1 << 2)	/* AC97 Unit Clock Enable */#define CKEN1_PWM1	(1 << 1)	/* PWM1 Clock Enable */#define CKEN0_PWM0	(1 << 0)	/* PWM0 Clock Enable */#define OSCC_OON	(1 << 1)	/* 32.768kHz OON (write-once only bit) */#define OSCC_OOK	(1 << 0)	/* 32.768kHz OOK (read-only bit) *///#ifdef CONFIG_MONAHANS#if 0/* * Core Clock */#define ACCR		__REG(0x41340000)  /* Application Subsystem Clock Configuration Register */#define ACSR		__REG(0x41340004)  /* Application Subsystem Clock Status Register */#define AICSR		__REG(0x41340008)  /* Application Subsystem Interrupt Control/Status Register */#define CKENA		__REG(0x4134000C)  /* A Clock Enable Register */#define CKENB		__REG(0x41340010)  /* B Clock Enable Register */#define AC97_DIV	__REG(0x41340014)  /* AC97 clock divisor value register *//* * ACCR: Application Subsystem Clock Configuration register */#define ACCR_XPDIS              (1 << 31)	/* 0x80000000 */#define ACCR_XPDIS_OFF          (0 << 31)#define ACCR_SPDIS              (1 << 30)	/* 0x40000000 */#define ACCR_SPDIS_OFF          (0 << 30)#define ACCR_13MEND1            (1 << 27)	/* 0x08000000 */#define ACCR_13MEND1_OFF        (0 << 27)#define ACCR_D0CS               (1 << 26)	/* 0x04000000 */#define ACCR_D0CS_OFF           (0 << 26)#define ACCR_SMCFS_MASK         0x03800000	/* Static Memory Controller Frequency Select */#define ACCR_SMCFS_104MHZ       0x01000000	/*  104MHz */#define ACCR_SMCFS_208MHZ       0x02800000	/*  208MHz */#define ACCR_13MEND2            (1 << 21)	/* 0x00200000 */#define ACCR_13MEND2_OFF        (0 << 21)#define ACCR_SFLFS_MASK         0x000c0000	/* SRAM Controller Frequency Select */#define ACCR_SFLFS_156MHZ       0x00040000	/*  156MHz */#define ACCR_SFLFS_208MHZ       0x00080000	/*  208MHz */#define ACCR_SFLFS_312MHZ       0x000c0000	/*  312MHz */#define ACCR_XSPCLK_MASK        0x00030000	/* XScale Core Frequency during Frequency Change */#define ACCR_XSPCLK_WAIT_LOCK   0x00030000	/*  No clock to core until XSC PLL is re-locked */#define ACCR_HSS_MASK           0x0000c000	/* High Speed IO Bus-Clock Frequency Select */#define ACCR_HSS_104MHZ         0x00000000	/*  104MHZ */#define ACCR_HSS_156MHZ         0x00004000	/*  156MHZ */#define ACCR_HSS_208MHZ         0x00008000	/*  208MHZ */#define ACCR_DMCFS_MASK         0x00003000	/* DDR Memory Controller Clock Frequency Select */#define ACCR_DMCFS_26MHZ        0x00000000	/*  26 MHZ */#define ACCR_DMCFS_260MHZ       0x00003000	/*  260MHZ */#define ACCR_PCCE               (1 << 11)	/* 0x00000800 */#define ACCR_PCCE_OFF           (0 << 11)#define ACCR_XN_MASK            0x00000700	/* XScale Core PLL Turbo-Mode-to-Run-Mode Ratio */#define ACCR_XN_T1_TO_R1        0x00000100	/*  Turbo-mode-to-run-mode ratio = 1:1 */#define ACCR_XN_T2_TO_R1        0x00000200	/*  Turbo-mode-to-run-mode ratio = 2:1 */#define ACCR_XN_T4_TO_R1        0x00000400	/*  Turbo-mode-to-run-mode ratio = 4:1 */#define ACCR_XL_MASK            0x0000001f	/* XScale Core PLL Run-Mode-to-Oscillator Ratio */#define ACCR_XL_R4_TO_O1        0x00000004	/*  Run-mode-to-oscillator ratio = 4:1 */#define ACCR_XL_R8_TO_O1        0x00000008	/*  Run-mode-to-oscillator ratio = 8:1 */#define ACCR_XL_R12_TO_O1       0x0000000c	/*  Run-mode-to-oscillator ratio = 12:1 */#define ACCR_XL_R16_TO_O1       0x00000010	/*  Run-mode-to-oscillator ratio = 16:1 */#define ACCR_XL_R24_TO_O1       0x00000018	/*  Run-mode-to-oscillator ratio = 24:1 */#define ACCR_XL_R31_TO_O1       0x0000001f	/*  Run-mode-to-oscillator ratio = 31:1 *//* * XCLKCFG: Intel XScale Core Clock Congiguration Register */#define XCLKCFG_F       (1 << 1)	/* 0x00000002: Intel XScale Core Frequency Change */#define XCLKCFG_F_OFF   (0 << 1)	#define XCLKCFG_T       (1 << 0)	/* 0x00000001: Turbo mode */#define XCLKCFG_T_OFF   (0 << 0)	/* * D0CKEN_A and D0CKEN_B: D0 Mode Clock Enable registers */#define CKENA_30_MSL0	(1 << 30) 	/* MSL0 Interface Unit Clock Enable */#define CKENA_29_SSP4	(1 << 29) 	/* SSP3 Unit Clock Enable */#define CKENA_28_SSP3	(1 << 28) 	/* SSP2 Unit Clock Enable */#define CKENA_27_SSP2	(1 << 27)  	/* SSP1 Unit Clock Enable */#define CKENA_26_SSP1	(1 << 26)	/* SSP0 Unit Clock Enable */#define CKENA_25_TSI	(1 << 25)	/* TSI Clock Enable */#define CKENA_24_AC97	(1 << 24)	/* AC97 Unit Clock Enable */#define CKENA_23_STUART	(1 << 23)	/* STUART Unit Clock Enable */#define CKENA_22_FFUART	(1 << 22)	/* FFUART Unit Clock Enable */#define CKENA_21_BTUART	(1 << 21)	/* BTUART Unit Clock Enable */#define CKENA_20_UDC	(1 << 20)	/* UDC Clock Enable */#define CKENA_19_TPM	(1 << 19) 	/* TPM Unit Clock Enable */#define CKENA_18_USIM1	(1 << 18) 	/* USIM1 Unit Clock Enable */#define CKENA_17_USIM0	(1 << 17) 	/* USIM0 Unit Clock Enable */#define CKENA_15_CIR	(1 << 15) 	/* Consumer IR Clock Enable */#define CKENA_14_KEY	(1 << 14) 	/* Keypad Controller Clock Enable */#define CKENA_13_MMC1	(1 << 13) 	/* MMC1 Clock Enable */#define CKENA_12_MMC0	(1 << 12) 	/* MMC0 Clock Enable */#define CKENA_11_FLASH	(1 << 11) 	/* Boot ROM Clock Enable */#define CKENA_10_SRAM	(1 << 10) 	/* SRAM Controller Clock Enable */#define CKENA_9_SMC	(1 << 9) 	/* Static Memory Controller */#define CKENA_8_DMC	(1 << 8) 	/* Dynamic Memory Controller */#define CKENA_7_GRAPHICS (1 << 7) 	/* 2D Graphics Clock Enable */#define CKENA_6_USBCLI	(1 << 6)	/* USB Client Unit Clock Enable */#define CKENA_4_NAND	(1 << 4) 	/* NAND Flash Controller Clock Enable */#define CKENA_3_CAMERA	(1 << 3) 	/* Camera Interface Clock Enable */#define CKENA_2_USBHOST	(1 << 2)	/* USB Host Unit Clock Enable */#define CKENA_1_LCD	(1 << 1)	/* LCD Unit Clock Enable */#define CKENB_8_1WIRE	((1 << 8) + 32) /* One Wire Interface Unit Clock Enable */#define CKENB_7_GPIO	((1 << 7) + 32) 	/* GPIO Clock Enable */#define CKENB_6_IRQ	((1 << 6) + 32) 	/* Interrupt Controller Clock Enable */#define CKENB_4_I2C	((1 << 4) + 32)	/* I2C Unit Clock Enable */#define CKENB_1_PWM1	((1 << 1) + 32)	/* PWM2 & PWM3 Clock Enable */#define CKENB_0_PWM0	((1 << 0) + 32)	/* PWM0 & PWM1 Clock Enable *//*  * \TODO: Need to figure out CKEN scheme between old PXA and Monahans. * For now, we'll just add defines without the bit number and make * some bogus ones up for Monahans.   * * * The Monahans clock enable code is completely bogus anyway (they * re-arranged the CKEN stuff for Monahans, so we can't just use the * old code).   * * A possible solution we could use: * - Change CKEN defines to just be a number rather than a bitmask *   (this is needed since there are now up to 64) * - Change the code that uses the CKEN bits to deal with this * - Delete the old #defines. */#define CKEN_LCD	(0xFFFFFFFF)	/* LCD Unit Clock Enable */#define CKEN_BTUART	(0xFFFFFFFF)	/* BTUART Unit Clock Enable */#define CKEN_FFUART	(0xFFFFFFFF)	/* FFUART Unit Clock Enable */#define CKEN_STUART	(0xFFFFFFFF)	/* STUART Unit Clock Enable */// Power Management#define ASCR		__REG(0x40F40000)  /* Application Subsystem Power Status/Control Register */#define ARSR		__RE