/* *  blob/include/arch/s3c2500-regs.h *   *  Copyright (C) 2003  Russ Dill <Russ.Dill@asu.edu> * * Original Copyright:  *  Author:	Nicolas Pitre *  Created:	Jun 15, 2001 *  Copyright:	MontaVista Software Inc. *   * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */#ifndef _S3C2500_REGS_H_#define _S3C2500_REGS_H_#include <blob/proc/s3c2500.h>/* Get the M value for a speed in MHz a P, and an S */#define Fin 	10/* The +(Fin - 1) thing is so it rounds up */#define PLL_CALC_M(Fout, s, p) \	(((p + 2) * (1 << s) * Fout + (Fin - 1)) / Fin - 8)/* get the whole kit-n-kaboodle */#define PLL_VALUE(Fout, s, p) \	(PLL_S(s) | PLL_P(p) | PLL_M(PLL_CALC_M(Fout, s, p)))/* get the MHz as a number */#define GET_PLL_S(x)	((x >> 16) & 0x3) #define GET_PLL_P(x)	((x >> 8) & 0x3f)#define GET_PLL_M(x)	((x >> 0) & 0xff)#define _GET_MHz(s, p, m) \	((Fin * (m + 8)) / ((p + 2) * (1 << s))) #define GET_MHz(x) \	_GET_MHz(GET_PLL_S(x), GET_PLL_P(x), GET_PLL_M(x))/* PLL defines for a 10MHz input */#define SPEED_33MHz	PLL_VALUE(33, 1, 3)#define SPEED_48MHz	PLL_VALUE(48, 3, 3)#define SPEED_50HMz	PLL_VALUE(50, 1, 3)#define SPEED_66MHz	PLL_VALUE(66, 1, 2)#define SPEED_96MHz	PLL_VALUE(96, 3, 2)#define SPEED_100MHz	PLL_VALUE(100, 1, 2)#define SPEED_125MHz	PLL_VALUE(125, 1, 1)#define SPEED_133MHz	PLL_VALUE(133, 1, 1)#define SPEED_150MHz	PLL_VALUE(150, 1, 1)#define SPEED_166MHz	PLL_VALUE(166, 3, 1)#define SPEED_200MHz	PLL_VALUE(200, 1, 1)#define SPEED_233MHz	PLL_VALUE(233, 1, 1)#define SPEED_266MHz	PLL_VALUE(266, 1, 0)#define SPEED_300MHz	PLL_VALUE(300, 1, 0)/* * S3C2500 Chip selects */#define S3C2500_CS0_PHYS	0x00000000#define S3C2500_CS1_PHYS	0x01000000#define S3C2500_CS2_PHYS	0x02000000#define S3C2500_CS3_PHYS	0x03000000#define S3C2500_CS4_PHYS	0x04000000#define S3C2500_CS5_PHYS	0x05000000#define S3C2500_CS6_PHYS	0x06000000#define S3C2500_CS7_PHYS	0x07000000/* * S3C2500 SDRAM banks */#define S3C2500_SDRAM_BANK0	0x40000000#define S3C2500_SDRAM_BANK1	0x80000000#define ASIC_BASE		0xF0000000/* * System config */#define SYSCFG_BASEB	0x00000000#define SYSCFG_BASE	(ASIC_BASE + SYSCFGB)#define SYSCFG		__REG2(SYSCFG_BASE,0x00) /* System configuration */#define CPLLREN		(1 << 31)#define SPLLREN		(1 << 30)#define UPLLREN		(1 << 29)#define PPLLREN		(1 << 28)#define CPLLCE		(1 << 27)#define SPLLCE		(1 << 26)#define UPLLCE		(1 << 25)#define PPLLCE		(1 << 24)#define BIG_ENDIAN	(1 << 16)#define REMAP		(1 << 8)#define HCLK0_DIS	(1 << 4)#define ARB		(1 << 0)#define PDCODE		__REG2(SYSCFG_BASE,0x04) /* Product code */#define CLKCON		__REG2(SYSCFG_BASE,0x08) /* System clock control */#define PCLKDIS		__REG2(SYSCFG_BASE,0x0c) /* Peripheral clock disable */#define CLKST		__REG2(SYSCFG_BASE,0x10) /* Clock status */#define HPRIF		__REG2(SYSCFG_BASE,0x14) /* AHB fixed priority */#define HPRIR		__REG2(SYSCFG_BASE,0x18) /* AHB round-robin */#define CPLL		__REG2(SYSCFG_BASE,0x1c) /* Core PLL config */#define SPLL		__REG2(SYSCFG_BASE,0x20) /* Bus PLL config */#define UPLL		__REG2(SYSCFG_BASE,0x24) /* USB PLL config */#define PPLL		__REG2(SYSCFG_BASE,0x28) /* PHY PLL config */#define	PLL_S(x)	(x << 16)#define PLL_P(x)	(x << 8)#define PLL_M(x)	(x << 0)/* * Memory Controller *//* I/O Banks */#define BCONB		0x00010000#define BCON		(ASIC_BASE + BCONB)#define B0CON		__REG2(BCON,0x00)#define B1CON		__REG2(BCON,0x04)#define B2CON		__REG2(BCON,0x08)#define B3CON		__REG2(BCON,0x0c)#define B4CON		__REG2(BCON,0x10)#define B5CON		__REG2(BCON,0x14)#define B6CON		__REG2(BCON,0x18)#define B7CON		__REG2(BCON,0x1c)#define TCOH(x)		(x << 0)#define TCOS(x)		(x << 4)#define TACS(x)		(x << 8)#define TPA(x)		(x << 12) /* tACC of accesses where nOE and nRCS				   * is held low, and just the address 				   * is changed (page read) */#define TACC(x)		(x << 16)#define IS		(1 << 23)#define BS(x)		(x << 24)#define PMC(x)		(x << 28)#define PMC4		PMC(1)#define PMC8		PMC(2)#define PMC16		PMC(3)#define DW(x)		(x << 30)#define DW8		DW(1)#define DW16		DW(2)#define DW32		DW(3)#define MUXBCON		__REG2(BCON,0x20)#define WAITCON		__REG2(BCON,0x24)/* SDRAM controller */#define SDRAMB		0x00020000#define SDRAM		(ASIC_BASE + SDRAMB)#define CFGREG		__REG2(SDRAM,0x00)#define XW		(1 << 0)#define XW16		(XW)#define XW32		(0)#define NO_AP		(1 << 1)#define AP		(0)#define CL(x)		(x << 2)#define D1(x)		(x << 4)#define D1_16M		D1(0)#define D1_64M		D1(1)#define D1_128M		D1(2)#define D1_256M		D1(3)#define D0(x)		(x << 6)#define D0_16M		D0(0)#define D0_64M		D0(1)#define D0_128M		D0(2)#define D0_256M		D0(3)#define RP(x)		((x - 1) << 8)#define RCD(x)		((x - 1) << 10)#define RC(x)		((x - 1) << 12)#define RAS(x)		((x - 1) << 16)#define CMDREG		__REG2(SDRAM,0x04)#define INIT(x)		(x << 0)#define PALL		INIT(1)#define MRS		INIT(2)#define WBUF		(1 << 2)#define BUSY		(1 << 3)#define REFREG		__REG2(SDRAM,0x08)#define WBTOREG		__REG2(SDRAM,0x0c)/* * UARTs *//* Console UART (CUART) */#define CUARTB		0x00060000#define CUART		(ASIC_BASE + CUARTB)#define CUCON		__REG2(CUART,0x00) /* Control register (rw) */#define CUSTAT		__REG2(CUART,0x04) /* Status register (rw) */#define CUINT		__REG2(CUART,0x08) /* Interrupt enable register (rw) */#define CUTXBUF		__REG2(CUART,0x0C) /* Transmit buffer (wronly) */#define CURXBUF		__REG2(CUART,0x10) /* receive buffer (rdonly) */#define CUBRD		__REG2(CUART,0x14) /* Badu rate divisor register (rw) */#define CUCHAR1		__REG2(CUART,0x18) /* UART control char register 1 (rw) */#define CUCHAR2		__REG2(CUART,0x1C) /* UART control char register 2 (rw) */#define CUCON_TMODE	(1 << 0)	/* Transmitter enable */#define CUCON_RMODE	(1 << 2)	/* Receiver enable */#define CUCON_SBR	(1 << 4)	/* Send break */#define CUCON_SCSEL	(1 << 5)	/* Enable external clock */#define CUCON_LOOPB	(1 << 7)	/* loopback */#define CUCON_PODD	(4 << 8)	/* odd parity */#define CUCON_PEVEN	(5 << 8)	/* even parity */#define CUCON_STB	(1 << 11)	/* two stop bits */#define CUCON_5BITS	(0 << 12)	/* 5 bits */#define CUCON_6BITS	(1 << 12)	/* 6 bits */#define CUCON_7BITS	(2 << 12)	/* 7 bits */#define CUCON_8BITS	(3 << 12)	/* 8 bits */#define CUCON_IR	(1 << 14)	/* IR mode */#define CUCON_SFEN	(1 << 29)	/* Software flow control */#define CUCON_ECHO	(1 << 30)	/* Echo mode enable */#define CUSTAT_RDV	(1 << 0)	/* Receive data valid */#define CUSTAT_BSD	(1 << 1)	/* Break signal detected */#define CUSTAT_FER	(1 << 2)	/* Framing error */#define CUSTAT_PER	(1 << 3)	/* Parity Error */#define CUSTAT_OER	(1 << 4)	/* Overrun error */#define CUSTAT_CCD	(1 << 5)	/* Control character detected */#define CUSTAT_RXIDLE	(1 << 11)	/* Receiver in idle */#define CUSTAT_TI	(1 << 17)	/* Transmitter idle */#define CUSTAT_THE	(1 << 18)	/* Transmit holding register empty *//* * General Purpose I/O */#define IOPB		0x00030000#define IOP		(ASIC_BASE + IOPB)#define IOPMODE1	__REG2(IOP, 0x00)#define IOPMODE2	__REG2(IOP, 0x04)#define IOPCON1		__REG2(IOP, 0x08)#define IOPCON2		__REG2(IOP, 0x0C)#define IOPGDMA		__REG2(IOP, 0x10)#define IOPEXTINT	__REG2(IOP, 0x14)#define IOPEXTINTPND	__REG2(IOP, 0x18)#define IOPDATA1	__REG2(IOP, 0x1C)#define IOPDATA2	__REG2(IOP, 0x20)#define IOPDRV1		__REG2(IOP, 0x24)#define IOPDRV2		__REG2(IOP, 0x28)/* * Interrupt controller */#define INTCFGB		0x00140000#define INTCFG		(ASIC_BASE + INTCFGB)#define INTMOD		__REG2(INTCFG,0x00)#define EXTMOD		__REG2(INTCFG,0x04)#define INTMASK		__REG2(INTCFG,0x08)#define INTMASK_ALL	(0xffffffff)#define EXTMASK		__REG2(INTCFG,0x0c)#define EXTMASK_ALL	(0x0000007f)#define IPRIORHI	__REG2(INTCFG,0x10)#define IPRIORLO	__REG2(INTCFG,0x14)#define INTOFFSET_FIQ	__REG2(INTCFG,0x18)#define INTOFFSET_IRQ	__REG2(INTCFG,0x1c)#define INTPRIOR0	__REG2(INTCFG,0x20)#define INTPRIOR1	__REG2(INTCFG,0x24)#define INTPRIOR2	__REG2(INTCFG,0x28)#define INTPRIOR3	__REG2(INTCFG,0x2c)#define INTPRIOR4	__REG2(INTCFG,0x30)#define INTPRIOR5	__REG2(INTCFG,0x34)#define INTPRIOR6	__REG2(INTCFG,0x38)#define INTPRIOR7	__REG2(INTCFG,0x3c)#define INTPRIOR8	__REG2(INTCFG,0x40)#define INTPRIOR9	__REG2(INTCFG,0x44)#define INTTSTHI	__REG2(INTCFG,0x48)#define INTTSTLO	__REG2(INTCFG,0x4c)/* * Timers */#define TIMER_BASEB	0x00040000#define TIMER_BASE	(ASIC_BASE + TIMER_BASEB)#define TMOD		__REG2(TIMER_BASE, 0x00)#define TDATA0		__REG2(TIMER_BASE, 0x10)#define TDATA1		__REG2(TIMER_BASE, 0x18)#define TDATA2		__REG2(TIMER_BASE, 0x20)#define TDATA3		__REG2(TIMER_BASE, 0x28)#define TDATA4		__REG2(TIMER_BASE, 0x30)#define TDATA5		__REG2(TIMER_BASE, 0x38)#define TCNT0		__REG2(TIMER_BASE, 0x14)#define TCNT1		__REG2(TIMER_BASE, 0x1C)#define TCNT2		__REG2(TIMER_BASE, 0x24)#define TCNT3		__REG2(TIMER_BASE, 0x2C)#define TCNT4		__REG2(TIMER_BASE, 0x34)#define TCNT5		__REG2(TIMER_BASE, 0x3C)#define TIC		__REG2(TIMER_BASE, 0x04)#define WDT		__REG2(TIMER_BASE, 0x08)#define TIMER_TE0	(1 << 0)#define TIMER_TMD0	(1 << 1)#define TIMER_CLR0	(1 << 2)#define TIMER_TE1	(1 << 3)#define TIMER_TMD1	(1 << 4)#define TIMER_CLR1	(1 << 5)#define TIMER_TE2	(1 << 6)#define TIMER_TMD2	(1 << 7)#define TIMER_CLR2	(1 << 8)#define TIMER_TE3	(1 << 9)#define TIMER_TMD3	(1 << 10)#define TIMER_CLR3	(1 << 11)#define TIMER_TE4	(1 << 12)#define TIMER_TMD4	(1 << 13)#define TIMER_CLR4	(1 << 14)#define TIMER_TE5	(1 << 15)#define TIMER_TMD5	(1 << 16)#define TIMER_CLR5	(1 << 17)#endif