#include  "boothwi_6000.h" 
#include  "msm6000reg.h"
#include  "msm6000bits.h"
#include  "msm6000redefs.h"


typedef  unsigned char     byte;         /* Unsigned 8  bit value type. */
typedef  unsigned short    word;         /* Unsinged 16 bit value type. */
typedef  unsigned long     dword;        /* Unsigned 32 bit value type. */

#define TRUE   1   /* Boolean true value. */
#define FALSE  0   /* Boolean false value. */

#define  ON   1    /* On value. */
#define  OFF  0    /* Off value. */
#define NULL  0



  /* ARM based targets use memory mapped i/o, so the inp/outp calls are
  ** macroized to access memory directly
  */
  #define inp(port)         (*((volatile byte *) (port)))
  #define inpw(port)        (*((volatile word *) (port)))
  #define inpdw(port)       (*((volatile dword *)(port)))
  
  #define outp(port, val)   (*((volatile byte *) (port)) = ((byte) (val)))
  #define outpw(port, val)  (*((volatile word *) (port)) = ((word) (val)))
  #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val)))






#ifndef BOOTHW_6000_H
#define BOOTHW_6000_H

typedef struct {
    dword  addr;
    word   val;
}GpioFuncSelType;

typedef struct {
    dword  addr;
    word   val;
}ChipxnSelType;

/*----------------------------------------------------------------------------
  EXTERNAL MACROS
----------------------------------------------------------------------------*/

/*---------------------------------------------------------------------------

                    MACRO BOOTHW_KICK_WATCHDOG

This macro resets the watchdog timer circuit.
---------------------------------------------------------------------------*/
#define BOOTHW_KICK_WATCHDOG() \
      outp(SLEEP_CTL_WB, SLEEP_CTL_WB__WATCH_DOG_MASK); \
      outp(SLEEP_CTL_WB, 0)    
 
#endif /*BOOTHW_6000_H*/
 
 
 
 
/* TCXO frequencies */
#define BSP_TCXO_19P2_MHZ    19200  /* Khz, 19.2  Mhz */
#define BSP_TCXO_19P8_MHZ    19800  /* Khz, 19.8  Mhz */
#define BSP_TCXO_19P68_MHZ   19680  /* Khz, 19.68 Mhz */
/* TCXO frequency used in KHz */
#define BSP_TCXO_FREQUENCY_IN_KHZ   BSP_TCXO_19P2_MHZ
/* Sleep frequency used in KHz */
#define BSP_SLEEP_FREQUENCY_IN_KHZ   32
      

#define BOOT_HW_TCXO_SEL  MSM_CLK_CTL4_WH__TCXO_SEL_1920




#define MSM_BASE          CHIP_BASE             /* Base MSM Memory Mapped address */

#define MSM_INX( io ) (((io) - MSM_BASE)/4)



#define MSM_OUTHM_NO_INTLOCK( io, mask, val) \
  MSM_image_H[MSM_INX(io)] = (MSM_image_H[ MSM_INX( io ) ] & (word)(~(mask))) | \
         ((word)((val) & (mask)));\
  (void) outpw( io, ((word)MSM_image_H[ MSM_INX( io ) ]));\


#define MSM_OUTHM( io, mask, val) \
  MSM_OUTHM_NO_INTLOCK( io, mask, val);

  
#define ASB_INX( io ) (((io) - ASB_SHADOW_BASE)/4)

#define ASB_SHADOW_BASE   GPIO_INT_ADDR_SEL_WH  /* Base ASB Memory Mapped address */

#define ASB_END           (GPIO_INT_ADDR_SEL_WH + 4) 

#define ASB_MAX_INX       (((ASB_END - ASB_SHADOW_BASE)/4) + 1)


word ASB_image_H[ASB_MAX_INX];
/*---------------------------------------------------------------------------
                           MACRO ASB_OUTHM

This macro outputs a specified value, qualified by a specified mask, to
a specified port address. Only the bits corresponding to the mask are
actually affected; other bits retain their previous values. To do this,
an image is maintained of the previous value written to the port which
is then combined with the new value. This is used to output to 16bit locations.
The image maintained is also 16bits.
---------------------------------------------------------------------------*/
#define ASB_OUTHM( io, mask, val) \
  ASB_image_H[ASB_INX(io)] = (ASB_image_H[ ASB_INX( io ) ] & (word)(~(mask))) | \
         ((word)((val) & (mask)));\
  (void) outpw( io, ((word)ASB_image_H[ ASB_INX( io ) ]));
  
  
  
  
  
  
  
  
  #define RAM_SIZE         0x000FFFFF  /* RAM size - currently 1 Mbyte */



/* 
 * Specifies size of Device on ROM_CS_N and EEPROM_CS_N.  For values less than
 * size specified below *256k, ROM_CS_N will be asserted.  For address values
 * greater than or equal to specified side, EEPROM_CS_N will be asserted.
*/
#define ROM2_BASE     8         /* 2 Mbyte */



/* 
 * Specifies size of Device on RAM_CS_N and PCS6_N.  For values less than
 * size specified below * 256k, RAM_CS_N will be asserted.  For address values
 * greater than or equal to specified side, PCS6_N (RAM2_CS_N) will be
 * asserted.
*/
#define  RAM2_BASE    4         /* 1 Mbyte */


                                  
/***************************************************************************

                        Well-Known Memory Locations

***************************************************************************/

#define RAM_BASE         0x01000000  /* base of RAM */

#define IRQ_OFFSET       0x0000      /* offset from base of RAM to IRQ
                                        instruction that is vectored through
                                        RAM */

#define FIQ_OFFSET       0x0004      /* offset from base of RAM to FIQ 
                                        instruction that is vectored through
                                        RAM */

#define APP_ENTRY_POINT  0x00004000  /* entry into application space - Boot block
                                        reserves 16K */
                                      
#define MOB_MODEL_LOC    0x00000024  /* mobile model number location */

                                                    
/*----------------------------------------------------------------------------
               CHECK BLOCK SEGMENT & OFFSET POSITIONS

  The last bytes before the boot block segment are reserved for the check
  block.  The different items in the check block are located with different
  offsets from the beginning of the block.  The check block begins on a 16
  byte (segment) boundary.
----------------------------------------------------------------------------*/

#define ROM_CHECK_LOC            0x000FFFDC  /* check location for ROM test in 
                                                  boot sequence */
#define SEC_CODE_BYTES 8                     /* length of security code 
                                                (in bytes) */
#define SEC_CODE_LOC             0x000FFFE4  /* location in ROM of security 
                                                code */

/*----------------------------------------------------------------------------
                      ROM VALIDATION NUMBER VALUES

  The hex image flashed into ROM should have this value written at the
  location in the check block specified above.  This value is different
  for the different targets, so the wrong code can't get flashed in and
  still be considered valid.
----------------------------------------------------------------------------*/

#define ROM_CHECK_NUM 0x0001D     /* specific check value for SURF,
                                     NGP+MSM3 */