;------------------------------------------------------------------------------
; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv CN7PUE, 0x0007
         .equiv CN6PUE, 0x0006
         .equiv CN5PUE, 0x0005
         .equiv CN4PUE, 0x0004
         .equiv CN3PUE, 0x0003
         .equiv CN2PUE, 0x0002
         .equiv CN1PUE, 0x0001
         .equiv CN0PUE, 0x0000

;------------------------------------------------------------------------------
;     CNPU2 : Input Change Notification Pullup Enable Register 2
;------------------------------------------------------------------------------
; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv CN18PUE, 0x0002
         .equiv CN17PUE, 0x0001

;==============================================================================
;
; 4.  Timer Module Bit Position Definitions for SFRs
;     & SFR High/Low byte definitions.
;==============================================================================
; 4a. SFR Definitions
;------------------------------------------------------------------------------

;---------------Timer 1 Module-------------------------------------------------
         .equiv TMR1L, _TMR1
         .equiv TMR1H, _TMR1+1
         .equiv PR1L, _PR1
         .equiv PR1H, _PR1+1
         .equiv T1CONL, _T1CON                  ; See TxCON description in
         .equiv T1CONH, _T1CON+1                ;  sub-section below

;---------------Timer2/3 Module------------------------------------------------
         .equiv TMR2L, _TMR2
         .equiv TMR2H, _TMR2+1
         .equiv TMR3HLDL, _TMR3HLD
         .equiv TMR3HLDH, _TMR3HLD+1
         .equiv TMR3L, _TMR3
         .equiv TMR3H, _TMR3+1
         .equiv PR2L, _PR2
         .equiv PR2H, _PR2+1
         .equiv PR3L, _PR3
         .equiv PR3H, _PR3+1
         .equiv T2CONL, _T2CON                  ; See TxCON description in
         .equiv T2CONH, _T2CON+1                ;  sub-section below
         .equiv T3CONL, _T3CON                  ; - do -
         .equiv T3CONH, _T3CON+1

;-------------- Timer4/5 Module------------------------------------------------
         .equiv TMR4L, _TMR4
         .equiv TMR4H, _TMR4+1
         .equiv TMR5HLDL, _TMR5HLD
         .equiv TMR5HLDH, _TMR5HLD+1
         .equiv TMR5L, _TMR5
         .equiv TMR5H, _TMR5+1
         .equiv PR4L, _PR4
         .equiv PR4H, _PR4+1
         .equiv PR5L, _PR5
         .equiv PR5H, _PR5+1
         .equiv T4CONL, _T4CON                  ; See TxCON description in
         .equiv T4CONH, _T4CON+1                ;  sub-section below
         .equiv T5CONL, _T5CON                  ; - do -
         .equiv T5CONH, _T5CON+1

;-------------------------------------------------------------------------------
; 4b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
;     TxCON : Timer x Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv TON, 0x000F
         .equiv TSIDL, 0x000D

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv TGATE, 0x0006
         .equiv TCKPS1, 0x0005
         .equiv TCKPS0, 0x0004
         .equiv T32, 0x0003        ;T32 present only in T2CON and T4CON
         .equiv TSYNC, 0x0002
         .equiv TCS, 0x0001

;==============================================================================
;
; 5.  Quadrature Encoder Interface Module Bit Position Definitions for SFRs
;     & SFR High/Low byte definitions.
;==============================================================================
; 5a. SFR Definitions
;------------------------------------------------------------------------------
         .equiv QEICONL, _QEICON                ; See QEICON description in
         .equiv QEICONH, _QEICON+1              ;  sub-section below
         .equiv DFLTCONL, _DFLTCON              ; See DFLTCON description in
         .equiv DFLTCONH, _DFLTCON+1            ;  sub-section below
         .equiv POSCNTL, _POSCNT
         .equiv POSCNTH, _POSCNT+1
         .equiv MAXCNTL, _MAXCNT
         .equiv MAXCNTH, _MAXCNT+1

;------------------------------------------------------------------------------
; 5b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
;     QEICON : Quadrature Encoder Interface Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv CNTERR, 0x000F
         .equiv QEISIDL, 0x000D
         .equiv INDX, 0x000C
         .equiv UPDN, 0x000B
         .equiv QEIM2, 0x000A
         .equiv QEIM1, 0x0009
         .equiv QEIM0, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv SWPAB, 0x0007
         .equiv PCDOUT, 0x0006
         .equiv TQGATE, 0x0005
         .equiv TQCKPS1, 0x0004
         .equiv TQCKPS0, 0x0003
         .equiv POSRES, 0x0002
         .equiv TQCS, 0x0001
         .equiv UPDN_SRC, 0x0000

;------------------------------------------------------------------------------
;     DFLTCON : Digital Filter Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv IMV1, 0x000A
         .equiv IMV0, 0x0009
         .equiv CEID, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv QEOUT, 0x0007
         .equiv QECK2, 0x0006
         .equiv QECK1, 0x0005
         .equiv QECK0, 0x0004


;==============================================================================
;
; 6.  Input Capture Module Bit Position Definitions for SFRs
;     & SFR High/Low byte definitions.
;==============================================================================
; 6a. SFR Definitions
;------------------------------------------------------------------------------
         .equiv IC1BUFL, _IC1BUF
         .equiv IC1BUFH, _IC1BUF+1
         .equiv IC1CONL, _IC1CON                ; See ICxCON description in
         .equiv IC1CONH, _IC1CON+1              ;  sub-section below
         .equiv IC2BUFL, _IC2BUF
         .equiv IC2BUFH, _IC2BUF+1
         .equiv IC2CONL, _IC2CON                ; See ICxCON description in
         .equiv IC2CONH, _IC2CON+1              ;  sub-section below
         .equiv IC7BUFL, _IC7BUF
         .equiv IC7BUFH, _IC7BUF+1
         .equiv IC7CONL, _IC7CON                ; See ICxCON description in
         .equiv IC7CONH, _IC7CON+1              ;  sub-section below
         .equiv IC8BUFL, _IC8BUF
         .equiv IC8BUFH, _IC8BUF+1
         .equiv IC8CONL, _IC8CON                ; See ICxCON description in
         .equiv IC8CONH, _IC8CON+1              ;  sub-section below

;------------------------------------------------------------------------------
; 6b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
;     ICxCON : Input Capture x Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv ICSIDL, 0x000D

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv ICTMR, 0x0007
         .equiv ICI1, 0x0006
         .equiv ICI0, 0x0005
         .equiv ICOV, 0x0004
         .equiv ICBNE, 0x0003
         .equiv ICM2, 0x0002
         .equiv ICM1, 0x0001
         .equiv ICM0, 0x0000

;==============================================================================
;
; 7.  Output Compare Module Bit Position Definitions for SFRs
;     & SFR High/Low byte definitions.
;==============================================================================
; 7a. SFR Definitions
;------------------------------------------------------------------------------
         .equiv OC1RSL, _OC1RS
         .equiv OC1RSH, _OC1RS+1
         .equiv OC1RL, _OC1R
         .equiv OC1RH, _OC1R+1
         .equiv OC1CONL, _OC1CON                ; See OCxCON description in
         .equiv OC1CONH, _OC1CON+1              ;  sub-section below
         .equiv OC2RSL, _OC2RS
         .equiv OC2RSH, _OC2RS+1
         .equiv OC2RL, _OC2R
         .equiv OC2RH, _OC2R+1
         .equiv OC2CONL, _OC2CON                ; See OCxCON description in
         .equiv OC2CONH, _OC2CON+1              ;  sub-section below
         .equiv OC3RSL, _OC3RS
         .equiv OC3RSH, _OC3RS+1
         .equiv OC3RL, _OC3R
         .equiv OC3RH, _OC3R+1
         .equiv OC3CONL, _OC3CON                ; See OCxCON description in
         .equiv OC3CONH, _OC3CON+1              ;  sub-section below
         .equiv OC4RSL, _OC4RS
         .equiv OC4RSH, _OC4RS+1
         .equiv OC4RL, _OC4R
         .equiv OC4RH, _OC4R+1
         .equiv OC4CONL, _OC4CON                ; See OCxCON description in
         .equiv OC4CONH, _OC4CON+1              ;  sub-section below


;------------------------------------------------------------------------------
; 7b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
;     OCxCON : Output Compare x Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv OCSIDL, 0x000D

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv OCFLT, 0x0004
         .equiv OCTSEL, 0x0003
         .equiv OCM2, 0x0002
         .equiv OCM1, 0x0001
         .equiv OCM0, 0x0000

;==============================================================================
;
; 8. Motor Control PWM Module Bit Position Definitions for SFRs
;     & SFR High/Low byte definitions.
;==============================================================================
; 8a. SFR Definitions
;------------------------------------------------------------------------------
         .equiv PTCONL, _PTCON            ; See description for all registers
         .equiv PTCONH, _PTCON+1          ;  except PDCx registers, in section 8b
         .equiv PTMRL, _PTMR
         .equiv PTMRH, _PTMR+1
         .equiv PTPERL, _PTPER
         .equiv PTPERH, _PTPER+1
         .equiv SEVTCMPL, _SEVTCMP
         .equiv SEVTCMPH, _SEVTCMP+1
         .equiv PWMCON1L, _PWMCON1
         .equiv PWMCON1H, _PWMCON1+1
         .equiv PWMCON2L, _PWMCON2
         .equiv PWMCON2H, _PWMCON2+1
         .equiv DTCON1L, _DTCON1
         .equiv DTCON1H, _DTCON1+1
         .equiv FLTACONL, _FLTACON
         .equiv FLTACONH, _FLTACON+1
         .equiv OVDCONL, _OVDCON
         .equiv OVDCONH, _OVDCON+1
         .equiv PDC1L, _PDC1
         .equiv PDC1H, _PDC1+1
         .equiv PDC2L, _PDC2
         .equiv PDC2H, _PDC2+1
         .equiv PDC3L, _PDC3
         .equiv PDC3H, _PDC3+1

;------------------------------------------------------------------------------
; 8b. Bit Position Definitions for some SFRs
;------------------------------------------------------------------------------
;     PTCON : PWM Timebase Control Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv PTEN, 0x000F
         .equiv PTSIDL, 0x000D

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv PTOPS3, 0x0007
         .equiv PTOPS2, 0x0006
         .equiv PTOPS1, 0x0005
         .equiv PTOPS0, 0x0004
         .equiv PTCKPS1, 0x0003
         .equiv PTCKPS0, 0x0002
         .equiv PTMOD1, 0x0001
         .equiv PTMOD0, 0x0000

;------------------------------------------------------------------------------
;     PTMR : PWM Timebase Count Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv PTDIR, 0x000F

;------------------------------------------------------------------------------
;     SEVTCMP : Special Event Compare Register
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv SEVTDIR, 0x000F

;------------------------------------------------------------------------------
;     PWMCON1 : PWM Control Register 1
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv PMOD3, 0x000A
         .equiv PMOD2, 0x0009
         .equiv PMOD1, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below:
         .equiv PEN3H, 0x0006
         .equiv PEN2H, 0x0005
         .equiv PEN1H, 0x0004
         .equiv PEN3L, 0x0002
         .equiv PEN2L, 0x0001
         .equiv PEN1L, 0x0000

;------------------------------------------------------------------------------
;     PWMCON2 : PWM Control Register 2
;------------------------------------------------------------------------------
; High Byte (Odd Address)
; Bit Positions defined below:
         .equiv SEVOPS3, 0x000B
         .equiv SEVOPS2, 0x000A
         .equiv SEVOPS1, 0x0009
         .equiv SEVOPS0, 0x0008

; Low Byte (Even Address)
; Bit Positions defined below: