?? decoder.v
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//////////////////////////////////////////////////////////////////////
//// ////
//// 8051 core decoder ////
//// ////
//// This file is part of the 8051 cores project ////
//// http://www.opencores.org/cores/8051/ ////
//// ////
//// Description ////
//// Main 8051 core module. decodes instruction and creates ////
//// control sigals. ////
//// ////
//// To Do: ////
//// nothing ////
//// ////
//// Author(s): ////
//// - Simon Teran, simont@opencores.org ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// ver: 1
//
module decoder (clk, rst, op_in, ram_rd_sel, ram_wr_sel, wr_bit, wr, src_sel1, src_sel2, src_sel3, alu_op, psw_set, cy_sel, imm_sel, pc_wr, pc_sel,
comp_sel, eq, rom_addr_sel, ext_addr_sel, wad2, rd, write_x, reti);
// clk clock
// rst reset
// op_in operation code
// ram_rd_sel select, whitch address will be send to ram for read
// ram_wr_sel select, whitch address will be send to ram for write
// wr write - if 1 then we will write to ram
// src_sel1 select alu source 1
// src_sel2 select alu source 2
// src_sel3 select alu source 3
// alu_op alu operation
// psw_set will we remember cy, ac, ov from alu
// cy_sel carry in alu select
// comp_sel compare source select
// eq compare result
// wr_bit if write bit addresable
// wad2 wrihe acc from destination 2
// imm_sel immediate select
// pc_wr pc write
// pc_sel pc select
// rom_addr_sel rom address select (alu destination or pc)
// ext_addr_sel external address select (dptr or Ri)
// rd read from rom
// write_x write to external rom
// reti return from interrupt
input clk, rst, eq;
input [7:0] op_in;
output ram_rd_sel, ram_wr_sel, src_sel1, src_sel2, psw_set, alu_op, cy_sel, imm_sel, wr, pc_wr, pc_sel, comp_sel, wr_bit;
output src_sel3, rom_addr_sel, ext_addr_sel, wad2, rd, reti, write_x;
reg reti, write_x;
reg [1:0] psw_set, ram_rd_sel, src_sel1, src_sel2, imm_sel, pc_sel, cy_sel;
reg [3:0] alu_op;
reg wr, wr_bit, src_sel3, rom_addr_sel, ext_addr_sel, pc_wr, wad2;
reg [2:0] comp_sel, ram_wr_sel;
//
// state if 2'b00 then normal execution, sle instructin that need more than one clock
// op instruction buffer
reg [1:0] state;
reg [7:0] op;
//
// if state = 2'b00 then read nex instruction
assign rd = !state[0] & !state[1];
//
// main block
// case of instruction set control signals
always @(rst or op_in or eq or state)
begin
if (rst) begin
ram_rd_sel = 2'bxx;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
imm_sel = `IDS_DC;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
src_sel3 = `AS3_DC;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
wad2 = `WAD_N;
end else begin
case (state)
2'b01: begin
casex (op)
`ACALL :begin
ram_rd_sel = 2'bxx;
ram_wr_sel = `RWS_SP;
src_sel1 = `ASS_IMM;
src_sel2 = 2'bxx;
alu_op = `ALU_NOP;
imm_sel = `IDS_PCH;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
comp_sel = `CSS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`AJMP : begin
ram_rd_sel = 2'bxx;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = 2'bxx;
alu_op = `ALU_NOP;
imm_sel = `IDS_DC;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
comp_sel = `CSS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`LCALL :begin
ram_rd_sel = 2'bxx;
ram_wr_sel = `RWS_SP;
src_sel1 = `ASS_IMM;
src_sel2 = 2'bxx;
alu_op = `ALU_NOP;
imm_sel = `IDS_PCH;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
comp_sel = `CSS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
default begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_N;
pc_sel = `PIS_DC;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DC;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
endcase
end
2'b10:
casex (op)
`CJNE_R : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = !eq;
pc_sel = `PIS_ALU;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DES;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`CJNE_I : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = !eq;
pc_sel = `PIS_ALU;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DES;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`CJNE_D : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = !eq;
pc_sel = `PIS_ALU;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DES;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`CJNE_C : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = !eq;
pc_sel = `PIS_ALU;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DES;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`DJNZ_R : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = eq;
pc_sel = `PIS_ALU;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DES;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`DJNZ_D : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = eq;
pc_sel = `PIS_ALU;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_DES;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`JB : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = eq;
pc_sel = `PIS_ALU;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_BIT;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`JBC : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_D;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b1;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = eq;
pc_sel = `PIS_ALU;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_BIT;
wr_bit = 1'b1;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`JC : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = eq;
pc_sel = `PIS_ALU;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_CY;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`JMP : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = `PCW_Y;
pc_sel = `PIS_ALU;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_BIT;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`JNB : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = !eq;
pc_sel = `PIS_ALU;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_BIT;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`JNC : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = !eq;
pc_sel = `PIS_ALU;
imm_sel = `IDS_DC;
src_sel3 = `AS3_DC;
comp_sel = `CSS_CY;
wr_bit = 1'b0;
wad2 = `WAD_N;
rom_addr_sel = `RAS_PC;
ext_addr_sel = `EAS_DC;
end
`JNZ : begin
ram_rd_sel = `RRS_DC;
ram_wr_sel = `RWS_DC;
src_sel1 = `ASS_DC;
src_sel2 = `ASS_DC;
alu_op = `ALU_NOP;
wr = 1'b0;
psw_set = `PS_NOT;
cy_sel = `CY_0;
pc_wr = !eq;
pc_sel = `PIS_ALU;
imm_sel = `IDS_DC;
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