?? _primary.vhd
字號:
library verilog;use verilog.vl_types.all;entity ext_addr_sel is port( clk : in vl_logic; \select\ : in vl_logic; write : in vl_logic; dptr_hi : in vl_logic_vector(7 downto 0); dptr_lo : in vl_logic_vector(7 downto 0); ri : in vl_logic_vector(7 downto 0); addr_out : out vl_logic_vector(15 downto 0) );end ext_addr_sel;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -