library verilog;use verilog.vl_types.all;entity ext_addr_sel is    port(        clk             : in     vl_logic;        \select\        : in     vl_logic;        write           : in     vl_logic;        dptr_hi         : in     vl_logic_vector(7 downto 0);        dptr_lo         : in     vl_logic_vector(7 downto 0);        ri              : in     vl_logic_vector(7 downto 0);        addr_out        : out    vl_logic_vector(15 downto 0)    );end ext_addr_sel;