library verilog;use verilog.vl_types.all;entity rom_addr_sel is    port(        clk             : in     vl_logic;        rst             : in     vl_logic;        \select\        : in     vl_logic;        des1            : in     vl_logic_vector(7 downto 0);        des2            : in     vl_logic_vector(7 downto 0);        pc              : in     vl_logic_vector(15 downto 0);        op1             : in     vl_logic_vector(7 downto 0);        out_data        : out    vl_logic_vector(7 downto 0);        out_addr        : out    vl_logic_vector(15 downto 0)    );end rom_addr_sel;