/* initialize the number of active mappings (sysPhysMemDescNumEnt) */    pMmu = &sysPhysMemDesc[0];    for (ix = 0; ix < NELEMENTS (sysPhysMemDesc); ix++)         if (pMmu->virtualAddr != (void *)DUMMY_VIRT_ADDR)            pMmu++;        else            break;    sysPhysMemDescNumEnt = ix;    /* initialize PCI library */#ifdef  INCLUDE_PCI    pciConfigLibInit (PCI_MECHANISM_1, PCI_CONFIG_ADDR, PCI_CONFIG_DATA, NONE);    sysPciIntInit ();			/* it does pciIntLibInit() *//***************wgr add it on 05.8.18 for the use of eee end ************/#ifdef  INCLUDE_EEV    syseeVPciInit ();#endif/*****************    end of wgr add ***************************/#endif /* INCLUDE_PCI */    /* initialize the PIC (Programmable Interrupt Controller) */    sysIntInitPIC ();		/* should be after the PCI init for IOAPIC */    intEoiGet = sysIntEoiGet;	/* function pointer used in intConnect () */    /* initialize PCI devices */#ifdef  INCLUDE_PCI#if (PCI_CFG_TYPE == PCI_CFG_AUTO)    /* Some boards don't have a typical BIOS     * for example, Intel's System Firmware Library needs pciAutoConfig      */    sysPciAutoConfig();#endif /* (PCI_CFG_TYPE == PCI_CFG_AUTO) */    /*      * PCI-to-PCI bridge initialization should be done here, if it is.     * It is not necessary for Intel 430HX PCISET, which splits     * the extended memory area as follows:     *   - Flash BIOS area from 4GByte to (4GB - 512KB)     *   - DRAM memory from 1MB to a maximum of 512MB     *   - PCI memory space from the top of DRAM to (4GB - 512KB)     */#ifdef INCLUDE_NETWORK    /* initialize PCI network controllers starting from Bus 0 */     pciConfigForeachFunc (0, TRUE, (PCI_FOREACH_FUNC) sysNetPciInit, NULL);#endif /* INCLUDE_NETWORK */#if (defined(INCLUDE_SCSI) && defined(INCLUDE_AIC_7880))    sysAic7880PciInit ();#endif  /* INCLUDE_SCSI && INCLUDE_AIC_7880 */#endif /* INCLUDE_PCI */    /* initialize devices on the board if following SFL boot process */    #ifdef INCLUDE_IACSFL    {#   ifdef INCLUDE_CTB69000VGA    extern int  ctB69000VgaInit();#   endif /* INCLUDE_CTB69000VGA */        /* superIO - basic intialization */    #   ifdef INCLUDE_SMCFDC37B78X    smcFdc37b78xDevCreate ((void *) NULL); /* intialize superIO library */        /* enable only given devices on SuperIO chip */    smcFdc37b78xInit ((SMCFDC37B78X_FDD_EN | SMCFDC37B78X_COM1_EN |                       SMCFDC37B78X_COM2_EN | SMCFDC37B78X_LPT1_EN |                       SMCFDC37B78X_KBD_EN));    #   endif /* INCLUDE_SMCFDC37B78X */        /* PC console - initialization */    #   if defined(INCLUDE_PC_CONSOLE)    #   ifdef INCLUDE_SMCFDC37B78X        smcFdc37b78xKbdInit ();              /* Initialize Kbd on SuperIO */    #   endif /* INCLUDE_SMCFDC37B78X */    #   ifdef INCLUDE_CTB69000VGA        ctB69000VgaInit ();                  /* Initialize VGA card */    #   endif /* INCLUDE_CTB69000VGA */    #   endif /* INCLUDE_PC_CONSOLE */        }#endif /* INCLUDE_IACSFL */#ifdef INCLUDE_USB    /*     * Since the Pentium BSPs do not rely on pciAutoCfg, sysUsbOhciInit     * must be called to update the MMU mapping for the ohci device.     * Please Note: INCLUDE_USB is not supported for boot_rom images.     */    sysUsbOhciPciInit ();#endif /* INCLUDE_USB */    /* initializes the serial devices */    sysSerialHwInit ();      /* initialize serial data structure */#ifdef INCLUDE_WINDML    sysWindMLHwInit ();#endif /* INCLUDE_WINDML */#ifdef VX_POWER_MANAGEMENT    /*     * initializes Power Management Mode     * VX_POWER_MODE_DEFAULT is defined in config.h     */    vxPowerModeSet(VX_POWER_MODE_DEFAULT);#endif /* VX_POWER_MANAGEMENT */    }/********************************************************************************* sysHwInit2 - additional system configuration and initialization** This routine connects system interrupts and does any additional* configuration necessary.** RETURNS: N/A*/void sysHwInit2 (void)    {#if	defined (INCLUDE_ADD_BOOTMEM)    /*     * We memAddToPool some upper memory into any low memory     * x86 "rom" images pool.  The x86 low memory images reside     * from 0x8000 to 0xa0000.  By memAddToPool'ing some upper     * memory here, we allow devices a larger pool to swim within.     * (SPR#21338).  This is no longer performed in bootConfig.c     */#   if (ADDED_BOOTMEM_SIZE != 0x0)     /*     * if &end (compiler symbol) is in lower memory, then we assume      * this is a low memory image, and add some upper memory to the pool.     */     if ((UINT32)(&end) < 0x100000)        {        /* Only do this if there is enough memory. Default is 4MB min. */         if ((UINT32)(memTopPhys) >= (0x00200000 + ADDED_BOOTMEM_SIZE))            {            memAddToPool ((char *)memTopPhys - ADDED_BOOTMEM_SIZE,                          ADDED_BOOTMEM_SIZE);            }        }#   endif /* (ADDED_BOOTMEM_SIZE !=0) */#endif	/* INCLUDE_ADD_BOOTMEM defined */     /* connect sys clock interrupt and auxiliary clock interrupt*/#ifdef	INCLUDE_APIC_TIMER    (void)intConnect (INUM_TO_IVEC (INT_NUM_LOAPIC_TIMER), sysClkInt, 0);#   ifdef PIT0_FOR_AUX    (void)intConnect (INUM_TO_IVEC (INT_NUM_GET (PIT0_INT_LVL)), sysAuxClkInt, 0);#   else    (void)intConnect (INUM_TO_IVEC (INT_NUM_GET (RTC_INT_LVL)), sysAuxClkInt, 0);#   endif /* PIT0_FOR_AUX */#else    (void)intConnect (INUM_TO_IVEC (INT_NUM_GET (PIT0_INT_LVL)), sysClkInt, 0);    (void)intConnect (INUM_TO_IVEC (INT_NUM_GET (RTC_INT_LVL)), sysAuxClkInt, 0);#endif	/* INCLUDE_APIC_TIMER */    /* connect serial interrupt */      sysSerialHwInit2();    /* connect stray(spurious/phantom) interrupt */  #if     defined(VIRTUAL_WIRE_MODE)    (void)intConnect (INUM_TO_IVEC (INT_NUM_LOAPIC_SPURIOUS), sysStrayInt, 0);    (void)intConnect (INUM_TO_IVEC (INT_NUM_GET (LPT_INT_LVL)), sysStrayInt, 0);#elif   defined(SYMMETRIC_IO_MODE)    (void)intConnect (INUM_TO_IVEC (INT_NUM_LOAPIC_SPURIOUS), sysStrayInt, 0);#else    (void)intConnect (INUM_TO_IVEC (INT_NUM_GET (LPT_INT_LVL)), sysStrayInt, 0);    (void)intConnect (INUM_TO_IVEC (INT_NUM_GET (PIC_SLAVE_STRAY_INT_LVL)), 		      sysStrayInt, 0);#endif  /* defined(VIRTUAL_WIRE_MODE) */#ifdef	INCLUDE_PC_CONSOLE    /* connect keyboard Controller 8042 chip interrupt */    (void) intConnect (INUM_TO_IVEC (INT_NUM_GET (KBD_INT_LVL)), kbdIntr, 0);#endif	/* INCLUDE_PC_CONSOLE */#if	defined (TGT_CPU) && defined (SYMMETRIC_IO_MODE)    /* init IPI vectors, connect IPI handler up to IPI_MAX_HANDLERS (=8) */    ipiVecInit (INT_NUM_LOAPIC_IPI);    ipiConnect ((INT_NUM_LOAPIC_IPI + 0), ipiHandlerShutdown);    ipiConnect ((INT_NUM_LOAPIC_IPI + 1), ipiHandlerTscReset);    ipiConnect ((INT_NUM_LOAPIC_IPI + 2), ipiHandlerTlbFlush);#endif	/* defined (TGT_CPU) && defined (SYMMETRIC_IO_MODE) */    }#ifdef	LOCAL_MEM_AUTOSIZE/********************************************************************************* WRITE_MEMORY_TEST_PATTERN** This routine writes the memory test pattern used in the sysPhysMemTop()* memory auto-size algorithm.  12 bytes of data stored at <pTestAddr> are* written to <pSaveAddr> before a 12-byte test pattern is written to* <pTestAddr>.** RETURNS: N/a** SEE ALSO:  RESTORE_MEMORY_TEST_ADDRS()*/__inline__ static void WRITE_MEMORY_TEST_PATTERN    (    int * pTestAddr,    int * pSaveAddr    )    {    pSaveAddr[0] = pTestAddr[0];    pSaveAddr[1] = pTestAddr[1];    pSaveAddr[2] = pTestAddr[2];    pTestAddr[0] = TEST_PATTERN_A;    pTestAddr[1] = TEST_PATTERN_B;    pTestAddr[2] = TEST_PATTERN_C;    cacheFlush (DATA_CACHE, pTestAddr, 16);    }/********************************************************************************* RESTORE_MEMORY_TEST_ADDRS** This routine restores memory test locations which are modified in the* sysPhysMemTop() memory auto-size algorithm.  12 bytes of data stored at* <pSaveAddr> are written to <pTestAddr>.** RETURNS: N/a** SEE ALSO:  WRITE_MEMORY_TEST_PATTERN()*/__inline__ static void RESTORE_MEMORY_TEST_ADDRS    (    int *       pTestAddr,    const int * pSaveAddr    )    {    pTestAddr[0] = pSaveAddr[0];    pTestAddr[1] = pSaveAddr[1];    pTestAddr[2] = pSaveAddr[2];    }#endif	/* LOCAL_MEM_AUTOSIZE *//********************************************************************************* sysPhysMemTop - get the address of the top of physical memory** This routine returns the address of the first missing byte of memory,* which indicates the top of physical memory.** INTERNAL* The memory auto-size logic assumes that the manifest constant PHYS_MEM_MAX* specifies the total size in bytes of the processor's physical address space.* In the case of IA-32 processors, PHYS_MEM_MAX will be 4GB (2^32 bytes) or* 64GB (2^36 bytes) if the 36-bit Physical Address Extension (PAE) is enabled* on select processor models.  However, because the tool-chain and sysMemTop()* API are 32-bit, this routine currently will not auto-size a 36-bit address* space.  Moreover, this routine will not return the memory top of a platform* with a memory device using a full 2^32 bytes of address space, as the memory* top of such a device would be a 33-bit value.** When paging is used, the processor divides the linear address space into* fixed-size pages (of 4KB, 2MB, or 4MB in length) that can be mapped into* physical memory and/or disk storage.  The auto-size algorithm organizes* the physical address space using the same concept.  That is, rather than* treating the address space as an array of bytes, the memory auto-size* code treats the address space as an array of equal-sized pages.** The auto-size algorithm attempts to locate the base-address of the first* non-existant page address in the physical address space.  This is done by* writing, and then reading, a test pattern to each page base-address in the* address space.  If the test pattern is not read back from a page, it is* assumed that the address does not physically exist.** As the installed physical memory could be potentially quite large, the* auto-size code attempts a few optimizations, chief among these being a* binary (as opposed to linear) search of the page array (ie. address space).* An additional optimization is obtained by avoiding a search on memory* that _must_ exist; namely, the memory storing the VxWorks boot image or* RTOS image from whence this routine will execute.** In the case of VxWorks boot and RTOS images for IA-32, the last byte of the* image section loaded highest in memory is assumed to be indicated by the* address of a symbol, named <end>, which is typically supplied by the linker* (more precisely, the linker script) used to build the image.  The search* for remaining extant physical page addresses on the system will use the* address of the first page following the <end> symbol, or a page-aligned* address no lower than physical memory location 0x100000 (1Mb), as a lower* bound on the search.  All memory locations below physical address 0x100000* are assumed to be reserved existing target memory.** RETURNS:  The address of the top of physical memory.*/char * sysPhysMemTop (void)    {    PHYS_MEM_DESC * pMmu;       /* points to memory desc. table entries */    char            gdtr[6];    /* stores a copy of the GDT */    BOOL            found = FALSE;    if (memTopPhys != NULL)        {        return (memTopPhys);        }#ifdef	LOCAL_MEM_AUTOSIZE    {    /* Do not use a page-sized stride larger than 4Kb, as the end of usable     * memory could possibly be within a 2Mb or 4Mb page memory range.     */    const UINT32 pageSize = PAGE_SIZE_4KB;    /* The lower bound for the probe will be the page-aligned VxWorks     * end-of-image address, or a page-aligned address no less than     * the 1Mb physical address.     */    UINT8 * pPage = (UINT8 *) ROUND_UP (((UINT32)(&end) > 0x100000) ?                          (UINT32)(&end) : (0x100000), pageSize);