////  Copyright (c) 2003 Launchbird Design Systems, Inc.//  All rights reserved.//  //  Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met://    Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.//    Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.//  //  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,//  INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.//  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,//  OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;//  OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT//  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.//  //  //  Overview://  //    Performs a radix 2 Fast Fourier Transform.//    The FFT architecture is pipelined on a rank basis; each rank has its own butterfly and ranks are//    isolated from each other using memory interleavers.  This FFT can perform calcualations on continuous//    streaming data (one data set right after another).  More over, inputs and outputs are passed in pairs,//    doubling the bandwidth.  For instance, a 2048 point FFT can perform a transform every 1024 cycles.//  //  Interface://  //    Synchronization://      clock_c  : Clock input.//      enable_i : Synchronous enable.//      reset_i  : Synchronous reset.//  //    Inputs://      sync_i     : Input sync pulse must occur one frame prior to data input.//      data_0_i   : Input data 0.  Width is 2 * precision.  Real on the left, imag on the right.//      data_1_i   : Input data 1.  Width is 2 * precision.  Real on the left, imag on the right.//  //    Outputs://      sync_o     : Output sync pulse occurs one frame before data output.//      data_0_o   : Output data 0.  Width is 2 * precision.  Real on the left, imag on the right.//      data_1_o   : Output data 1.  Width is 2 * precision.  Real on the left, imag on the right.//  //  Built In Parameters://  //    FFT Points   = 2048//    Precision    = 18//  //  //  //  //  Generated by Confluence 0.6.3  --  Launchbird Design Systems, Inc.  --  www.launchbird.com//  //  Build Date : Fri Aug 22 08:49:36 CDT 2003//  //  Interface//  //    Build Name    : cf_fft_2048_18//    Clock Domains : clock_c  //    Vector Input  : enable_i(1)//    Vector Input  : reset_i(1)//    Vector Input  : sync_i(1)//    Vector Input  : data_0_i(36)//    Vector Input  : data_1_i(36)//    Vector Output : sync_o(1)//    Vector Output : data_0_o(36)//    Vector Output : data_1_o(36)//  //  //  `timescale 1 ns / 1 nsmodule cf_fft_2048_18 (clock_c, enable_i, reset_i, sync_i, data_0_i, data_1_i, sync_o, data_0_o, data_1_o);input  clock_c;input  enable_i;input  reset_i;input  sync_i;input  [35:0] data_0_i;input  [35:0] data_1_i;output sync_o;output [35:0] data_0_o;output [35:0] data_1_o;wire   n1;wire   [35:0] n2;wire   [35:0] n3;cf_fft_2048_18_1 s1 (clock_c, sync_i, data_0_i, data_1_i, enable_i, reset_i, n1, n2, n3);assign sync_o = n1;assign data_0_o = n2;assign data_1_o = n3;endmodulemodule cf_fft_2048_18_1 (clock_c, i1, i2, i3, i4, i5, o1, o2, o3);input  clock_c;input  i1;input  [35:0] i2;input  [35:0] i3;input  i4;input  i5;output o1;output [35:0] o2;output [35:0] o3;wire   s1_1;wire   [35:0] s1_2;wire   [35:0] s1_3;wire   s2_1;wire   [35:0] s2_2;wire   [35:0] s2_3;wire   s3_1;wire   [35:0] s3_2;wire   [35:0] s3_3;wire   s4_1;wire   [35:0] s4_2;wire   [35:0] s4_3;wire   s5_1;wire   [35:0] s5_2;wire   [35:0] s5_3;cf_fft_2048_18_25 s1 (clock_c, s3_1, s3_2, s3_3, i4, i5, s1_1, s1_2, s1_3);cf_fft_2048_18_8 s2 (clock_c, s1_1, s1_2, s1_3, i4, i5, s2_1, s2_2, s2_3);cf_fft_2048_18_6 s3 (clock_c, s4_1, s4_2, s4_3, i4, i5, s3_1, s3_2, s3_3);cf_fft_2048_18_5 s4 (clock_c, s5_1, s5_2, s5_3, i4, i5, s4_1, s4_2, s4_3);cf_fft_2048_18_2 s5 (clock_c, i1, i2, i3, i4, i5, s5_1, s5_2, s5_3);assign o3 = s2_3;assign o2 = s2_2;assign o1 = s2_1;endmodulemodule cf_fft_2048_18_2 (clock_c, i1, i2, i3, i4, i5, o1, o2, o3);input  clock_c;input  i1;input  [35:0] i2;input  [35:0] i3;input  i4;input  i5;output o1;output [35:0] o2;output [35:0] o3;wire   [71:0] n1;wire   n2;wire   n3;wire   [8:0] n4;wire   [8:0] n5;wire   [1:0] n6;wire   [35:0] n7;wire   [35:0] n8;wire   [35:0] n9;wire   [35:0] n10;wire   [35:0] n11;wire   [35:0] n12;wire   s13_1;wire   [71:0] s14_1;wire   s15_1;wire   s15_2;wire   [71:0] s15_3;wire   [9:0] s16_1;wire   s16_2;assign n1 = {i2, i3};assign n2 = s16_1[9];assign n3 = ~n2;assign n4 = {s16_1[8],  s16_1[7],  s16_1[6],  s16_1[5],  s16_1[4],  s16_1[3],  s16_1[2],  s16_1[1],  s16_1[0]};assign n5 = {n4[0],  n4[1],  n4[2],  n4[3],  n4[4],  n4[5],  n4[6],  n4[7],  n4[8]};assign n6 = {s15_2, s15_1};assign n7 = {s15_3[71],  s15_3[70],  s15_3[69],  s15_3[68],  s15_3[67],  s15_3[66],  s15_3[65],  s15_3[64],  s15_3[63],  s15_3[62],  s15_3[61],  s15_3[60],  s15_3[59],  s15_3[58],  s15_3[57],  s15_3[56],  s15_3[55],  s15_3[54],  s15_3[53],  s15_3[52],  s15_3[51],  s15_3[50],  s15_3[49],  s15_3[48],  s15_3[47],  s15_3[46],  s15_3[45],  s15_3[44],  s15_3[43],  s15_3[42],  s15_3[41],  s15_3[40],  s15_3[39],  s15_3[38],  s15_3[37],  s15_3[36]};assign n8 = {s15_3[35],  s15_3[34],  s15_3[33],  s15_3[32],  s15_3[31],  s15_3[30],  s15_3[29],  s15_3[28],  s15_3[27],  s15_3[26],  s15_3[25],  s15_3[24],  s15_3[23],  s15_3[22],  s15_3[21],  s15_3[20],  s15_3[19],  s15_3[18],  s15_3[17],  s15_3[16],  s15_3[15],  s15_3[14],  s15_3[13],  s15_3[12],  s15_3[11],  s15_3[10],  s15_3[9],  s15_3[8],  s15_3[7],  s15_3[6],  s15_3[5],  s15_3[4],  s15_3[3],  s15_3[2],  s15_3[1],  s15_3[0]};assign n9 = {s14_1[71],  s14_1[70],  s14_1[69],  s14_1[68],  s14_1[67],  s14_1[66],  s14_1[65],  s14_1[64],  s14_1[63],  s14_1[62],  s14_1[61],  s14_1[60],  s14_1[59],  s14_1[58],  s14_1[57],  s14_1[56],  s14_1[55],  s14_1[54],  s14_1[53],  s14_1[52],  s14_1[51],  s14_1[50],  s14_1[49],  s14_1[48],  s14_1[47],  s14_1[46],  s14_1[45],  s14_1[44],  s14_1[43],  s14_1[42],  s14_1[41],  s14_1[40],  s14_1[39],  s14_1[38],  s14_1[37],  s14_1[36]};assign n10 = {s14_1[35],  s14_1[34],  s14_1[33],  s14_1[32],  s14_1[31],  s14_1[30],  s14_1[29],  s14_1[28],  s14_1[27],  s14_1[26],  s14_1[25],  s14_1[24],  s14_1[23],  s14_1[22],  s14_1[21],  s14_1[20],  s14_1[19],  s14_1[18],  s14_1[17],  s14_1[16],  s14_1[15],  s14_1[14],  s14_1[13],  s14_1[12],  s14_1[11],  s14_1[10],  s14_1[9],  s14_1[8],  s14_1[7],  s14_1[6],  s14_1[5],  s14_1[4],  s14_1[3],  s14_1[2],  s14_1[1],  s14_1[0]};assign n11 = s13_1 ? n8 : n7;assign n12 = s13_1 ? n10 : n9;cf_fft_2048_18_35 s13 (clock_c, n6, i4, i5, s13_1);cf_fft_2048_18_4 s14 (clock_c, s16_2, n1, n2, n5, i4, i5, s14_1);cf_fft_2048_18_3 s15 (clock_c, s16_2, n1, n3, n5, i4, i5, s15_1, s15_2, s15_3);cf_fft_2048_18_26 s16 (clock_c, i1, i4, i5, s16_1, s16_2);assign o3 = n12;assign o2 = n11;assign o1 = s15_1;endmodulemodule cf_fft_2048_18_3 (clock_c, i1, i2, i3, i4, i5, i6, o1, o2, o3);input  clock_c;input  i1;input  [71:0] i2;input  i3;input  [8:0] i4;input  i5;input  i6;output o1;output o2;output [71:0] o3;wire   [8:0] n1;wire   [8:0] n2;reg    [8:0] n3;wire   n4;reg    n5;wire   [8:0] n6;wire   n7;wire   n8;wire   [71:0] n9;reg    [8:0] n9a;reg    [71:0] n9m [511:0];wire   n10;wire   [71:0] n11;reg    [8:0] n11a;reg    [71:0] n11m [511:0];reg    n12;wire   [71:0] n13;wire   n14;wire   s15_1;assign n1 = 9'b000000001;assign n2 = n3 + n1;initial n3 = 9'b000000000;always @ (posedge clock_c)  if (n14 == 1'b1)    n3 <= 9'b000000000;  else if (i5 == 1'b1)    n3 <= n2;assign n4 = ~s15_1;initial n5 = 1'b0;always @ (posedge clock_c)  if (i6 == 1'b1)    n5 <= 1'b0;  else if (i5 == 1'b1)    n5 <= i1;assign n6 = 9'b000000000;assign n7 = n3 == n6;assign n8 = i3 & n4;initial n9a = 9'b000000000;always @ (posedge clock_c)  if (i5 == 1'b1) begin    if (n8 == 1'b1)      n9m[i4] <= i2;    n9a <= n3;  endassign n9 = n9m[n9a];assign n10 = i3 & s15_1;initial n11a = 9'b000000000;always @ (posedge clock_c)  if (i5 == 1'b1) begin    if (n10 == 1'b1)      n11m[i4] <= i2;    n11a <= n3;  endassign n11 = n11m[n11a];initial n12 = 1'b0;always @ (posedge clock_c)  if (i6 == 1'b1)    n12 <= 1'b0;  else if (i5 == 1'b1)    n12 <= n4;assign n13 = n12 ? n11 : n9;assign n14 = i1 | i6;cf_fft_2048_18_32 s15 (clock_c, i1, i5, i6, s15_1);assign o3 = n13;assign o2 = n7;assign o1 = n5;endmodulemodule cf_fft_2048_18_4 (clock_c, i1, i2, i3, i4, i5, i6, o1);input  clock_c;input  i1;input  [71:0] i2;input  i3;input  [8:0] i4;input  i5;input  i6;output [71:0] o1;wire   [8:0] n1;wire   [8:0] n2;reg    [8:0] n3;wire   n4;wire   n5;wire   [71:0] n6;reg    [8:0] n6a;reg    [71:0] n6m [511:0];wire   n7;wire   [71:0] n8;reg    [8:0] n8a;reg    [71:0] n8m [511:0];reg    n9;wire   [71:0] n10;wire   n11;wire   s12_1;assign n1 = 9'b000000001;assign n2 = n3 + n1;initial n3 = 9'b000000000;always @ (posedge clock_c)  if (n11 == 1'b1)    n3 <= 9'b000000000;  else if (i5 == 1'b1)    n3 <= n2;assign n4 = ~s12_1;assign n5 = i3 & n4;initial n6a = 9'b000000000;always @ (posedge clock_c)  if (i5 == 1'b1) begin    if (n5 == 1'b1)      n6m[i4] <= i2;    n6a <= n3;  endassign n6 = n6m[n6a];assign n7 = i3 & s12_1;initial n8a = 9'b000000000;always @ (posedge clock_c)  if (i5 == 1'b1) begin    if (n7 == 1'b1)      n8m[i4] <= i2;    n8a <= n3;  endassign n8 = n8m[n8a];initial n9 = 1'b0;always @ (posedge clock_c)  if (i6 == 1'b1)    n9 <= 1'b0;  else if (i5 == 1'b1)    n9 <= n4;assign n10 = n9 ? n8 : n6;assign n11 = i1 | i6;cf_fft_2048_18_32 s12 (clock_c, i1, i5, i6, s12_1);assign o1 = n10;endmodulemodule cf_fft_2048_18_5 (clock_c, i1, i2, i3, i4, i5, o1, o2, o3);input  clock_c;input  i1;input  [35:0] i2;input  [35:0] i3;input  i4;input  i5;output o1;output [35:0] o2;output [35:0] o3;wire   n1;wire   [71:0] n2;reg    n3;reg    n4;reg    n5;reg    n6;wire   [8:0] n7;reg    [8:0] n8;reg    [8:0] n9;reg    [8:0] n10;reg    [8:0] n11;wire   n12;reg    n13;reg    n14;reg    n15;reg    n16;wire   n17;wire   [1:0] n18;wire   [35:0] n19;wire   [35:0] n20;wire   [35:0] n21;wire   [35:0] n22;wire   [35:0] n23;wire   [35:0] n24;wire   [35:0] s25_1;wire   [35:0] s25_2;wire   s26_1;wire   [71:0] s27_1;wire   s28_1;wire   s28_2;wire   [71:0] s28_3;wire   [9:0] s29_1;wire   s29_2;assign n1 = 1'b0;assign n2 = {s25_1, s25_2};initial n3 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n3 <= 1'b0;  else if (i4 == 1'b1)    n3 <= s29_2;initial n4 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n4 <= 1'b0;  else if (i4 == 1'b1)    n4 <= n3;initial n5 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n5 <= 1'b0;  else if (i4 == 1'b1)    n5 <= n4;initial n6 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n6 <= 1'b0;  else if (i4 == 1'b1)    n6 <= n5;assign n7 = {s29_1[9],  s29_1[8],  s29_1[7],  s29_1[6],  s29_1[5],  s29_1[4],  s29_1[3],  s29_1[2],  s29_1[1]};initial n8 = 9'b000000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n8 <= 9'b000000000;  else if (i4 == 1'b1)    n8 <= n7;initial n9 = 9'b000000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n9 <= 9'b000000000;  else if (i4 == 1'b1)    n9 <= n8;initial n10 = 9'b000000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n10 <= 9'b000000000;  else if (i4 == 1'b1)    n10 <= n9;initial n11 = 9'b000000000;always @ (posedge clock_c)  if (i5 == 1'b1)    n11 <= 9'b000000000;  else if (i4 == 1'b1)    n11 <= n10;assign n12 = s29_1[0];initial n13 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n13 <= 1'b0;  else if (i4 == 1'b1)    n13 <= n12;initial n14 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n14 <= 1'b0;  else if (i4 == 1'b1)    n14 <= n13;initial n15 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n15 <= 1'b0;  else if (i4 == 1'b1)    n15 <= n14;initial n16 = 1'b0;always @ (posedge clock_c)  if (i5 == 1'b1)    n16 <= 1'b0;  else if (i4 == 1'b1)    n16 <= n15;assign n17 = ~n16;assign n18 = {s28_2, s28_1};assign n19 = {s28_3[71],  s28_3[70],  s28_3[69],  s28_3[68],  s28_3[67],  s28_3[66],  s28_3[65],  s28_3[64],  s28_3[63],  s28_3[62],  s28_3[61],  s28_3[60],  s28_3[59],  s28_3[58],  s28_3[57],  s28_3[56],  s28_3[55],  s28_3[54],  s28_3[53],  s28_3[52],  s28_3[51],  s28_3[50],  s28_3[49],  s28_3[48],  s28_3[47],  s28_3[46],  s28_3[45],  s28_3[44],  s28_3[43],  s28_3[42],  s28_3[41],  s28_3[40],  s28_3[39],  s28_3[38],  s28_3[37],  s28_3[36]};assign n20 = {s28_3[35],  s28_3[34],  s28_3[33],  s28_3[32],  s28_3[31],  s28_3[30],  s28_3[29],  s28_3[28],  s28_3[27],  s28_3[26],  s28_3[25],  s28_3[24],  s28_3[23],  s28_3[22],  s28_3[21],  s28_3[20],  s28_3[19],  s28_3[18],  s28_3[17],  s28_3[16],  s28_3[15],  s28_3[14],  s28_3[13],  s28_3[12],  s28_3[11],  s28_3[10],  s28_3[9],  s28_3[8],  s28_3[7],  s28_3[6],  s28_3[5],  s28_3[4],  s28_3[3],  s28_3[2],  s28_3[1],  s28_3[0]};assign n21 = {s27_1[71],  s27_1[70],  s27_1[69],  s27_1[68],  s27_1[67],  s27_1[66],  s27_1[65],  s27_1[64],  s27_1[63],  s27_1[62],  s27_1[61],  s27_1[60],  s27_1[59],  s27_1[58],  s27_1[57],  s27_1[56],  s27_1[55],  s27_1[54],