sbit CP0FIF  = CPT0CN ^ 4;          /* COMPARATOR 0 FALLING EDGE INTERRUPT */
sbit CP0HYP1 = CPT0CN ^ 3;          /* COMPARATOR 0 POSITIVE HYSTERESIS 1  */
sbit CP0HYP0 = CPT0CN ^ 2;          /* COMPARATOR 0 POSITIVE HYSTERESIS 0  */
sbit CP0HYN1 = CPT0CN ^ 1;          /* COMPARATOR 0 NEGATIVE HYSTERESIS 1  */
sbit CP0HYN0 = CPT0CN ^ 0;          /* COMPARATOR 0 NEGATIVE HYSTERESIS 0  */

/*  CPT1CN  0x88 */
sbit CP1EN   = CPT1CN ^ 7;          /* COMPARATOR 1 ENABLE                 */
sbit CP1OUT  = CPT1CN ^ 6;          /* COMPARATOR 1 OUTPUT                 */
sbit CP1RIF  = CPT1CN ^ 5;          /* COMPARATOR 1 RISING EDGE INTERRUPT  */
sbit CP1FIF  = CPT1CN ^ 4;          /* COMPARATOR 1 FALLING EDGE INTERRUPT */
sbit CP1HYP1 = CPT1CN ^ 3;          /* COMPARATOR 1 POSITIVE HYSTERESIS 1  */
sbit CP1HYP0 = CPT1CN ^ 2;          /* COMPARATOR 1 POSITIVE HYSTERESIS 0  */
sbit CP1HYN1 = CPT1CN ^ 1;          /* COMPARATOR 1 NEGATIVE HYSTERESIS 1  */
sbit CP1HYN0 = CPT1CN ^ 0;          /* COMPARATOR 1 NEGATIVE HYSTERESIS 0  */

/*  CPT2CN  0x88 */
sbit CP2EN   = CPT2CN ^ 7;          /* COMPARATOR 2 ENABLE                 */
sbit CP2OUT  = CPT2CN ^ 6;          /* COMPARATOR 2 OUTPUT                 */
sbit CP2RIF  = CPT2CN ^ 5;          /* COMPARATOR 2 RISING EDGE INTERRUPT  */
sbit CP2FIF  = CPT2CN ^ 4;          /* COMPARATOR 2 FALLING EDGE INTERRUPT */
sbit CP2HYP1 = CPT2CN ^ 3;          /* COMPARATOR 2 POSITIVE HYSTERESIS 1  */
sbit CP2HYP0 = CPT2CN ^ 2;          /* COMPARATOR 2 POSITIVE HYSTERESIS 0  */
sbit CP2HYN1 = CPT2CN ^ 1;          /* COMPARATOR 2 NEGATIVE HYSTERESIS 1  */
sbit CP2HYN0 = CPT2CN ^ 0;          /* COMPARATOR 2 NEGATIVE HYSTERESIS 0  */

/*  SCON0  0x98 */
sbit SM00 = SCON0 ^ 7;              /* UART 0 MODE 0            */
sbit SM10 = SCON0 ^ 6;              /* UART 0 MODE 1            */
sbit SM20 = SCON0 ^ 5;              /* UART 0 MCE               */
sbit REN0 = SCON0 ^ 4;              /* UART 0 RX ENABLE         */
sbit TB80 = SCON0 ^ 3;              /* UART 0 TX BIT 8          */
sbit RB80 = SCON0 ^ 2;              /* UART 0 RX BIT 8          */
sbit TI0  = SCON0 ^ 1;              /* UART 0 TX INTERRUPT FLAG */
sbit RI0  = SCON0 ^ 0;              /* UART 0 RX INTERRUPT FLAG */

/*  SCON1  0x98 */
sbit S0MODE = SCON1 ^ 7;            /* UART 1 MODE              */	
sbit MCE1   = SCON1 ^ 5;            /* UART 1 MCE               */
sbit REN1   = SCON1 ^ 4;            /* UART 1 RX ENABLE         */
sbit TB81   = SCON1 ^ 3;            /* UART 1 TX BIT 8          */
sbit RB81   = SCON1 ^ 2;            /* UART 1 RX BIT 8          */
sbit TI1    = SCON1 ^ 1;            /* UART 1 TX INTERRUPT FLAG */
sbit RI1    = SCON1 ^ 0;            /* UART 1 RX INTERRUPT FLAG */

/*  IE  0xA8 */
sbit EA    = IE ^ 7;                /* GLOBAL INTERRUPT ENABLE      */	
sbit ET2   = IE ^ 5;                /* TIMER 2 INTERRUPT ENABLE     */
sbit ES0   = IE ^ 4;                /* UART0 INTERRUPT ENABLE       */
sbit ET1   = IE ^ 3;                /* TIMER 1 INTERRUPT ENABLE     */
sbit EX1   = IE ^ 2;                /* EXTERNAL INTERRUPT 1 ENABLE  */
sbit ET0   = IE ^ 1;                /* TIMER 0 INTERRUPT ENABLE     */
sbit EX0   = IE ^ 0;                /* EXTERNAL INTERRUPT 0 ENABLE  */

/*  IP  0xB8 */
sbit PT2   = IP ^ 5;                /* TIMER 2 PRIORITY					*/	
sbit PS    = IP ^ 4;                /* SERIAL PORT PRIORITY				*/
sbit PT1   = IP ^ 3;                /* TIMER 1 PRIORITY					*/
sbit PX1   = IP ^ 2;                /* EXTERNAL INTERRUPT 1 PRIORITY	*/
sbit PT0   = IP ^ 1;                /* TIMER 0 PRIORITY					*/
sbit PX0   = IP ^ 0;                /* EXTERNAL INTERRUPT 0 PRIORITY	*/		

/* SMB0CN 0xC0 */
sbit BUSY   = SMB0CN ^ 7;           /* SMBUS 0 BUSY                    */
sbit ENSMB  = SMB0CN ^ 6;           /* SMBUS 0 ENABLE                  */
sbit STA    = SMB0CN ^ 5;           /* SMBUS 0 START FLAG              */
sbit STO    = SMB0CN ^ 4;           /* SMBUS 0 STOP FLAG               */
sbit SI     = SMB0CN ^ 3;           /* SMBUS 0 INTERRUPT PENDING FLAG  */
sbit AA     = SMB0CN ^ 2;           /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
sbit SMBFTE = SMB0CN ^ 1;           /* SMBUS 0 FREE TIMER ENABLE       */
sbit SMBTOE = SMB0CN ^ 0;           /* SMBUS 0 TIMEOUT ENABLE          */

/* CAN0STA 0xC0 */
sbit BOFF   = CAN0STA ^ 7;          /* Bus Off Status                  */
sbit EWARN  = CAN0STA ^ 6;          /* Warning Status                  */ 
sbit EPASS  = CAN0STA ^ 5;          /* Error Passive                   */
sbit RXOK   = CAN0STA ^ 4;          /* Received Message Successfully   */
sbit TXOK   = CAN0STA ^ 3;          /* Transmit a Message Successfully */
sbit LEC2   = CAN0STA ^ 2;          /* Last error code bit 2           */
sbit LEC1   = CAN0STA ^ 1;          /* Last error code bit 1           */
sbit LEC0   = CAN0STA ^ 0;          /* Last error code bit            */

/*  TMR2CN  0xC8 */
sbit TF2   = TMR2CN ^ 7;            /* TIMER 2 OVERFLOW FLAG        */
sbit EXF2  = TMR2CN ^ 6;            /* TIMER 2 EXTERNAL FLAG        */
sbit EXEN2 = TMR2CN ^ 3;            /* TIMER 2 EXTERNAL ENABLE FLAG */	
sbit TR2   = TMR2CN ^ 2;            /* TIMER 2 ON/OFF CONTROL       */
sbit CT2   = TMR2CN ^ 1;            /* TIMER 2 COUNTER SELECT       */
sbit CPRL2 = TMR2CN ^ 0;            /* TIMER 2 CAPTURE SELECT       */

/*  TMR3CN  0xC8 */
sbit TF3   = TMR3CN ^ 7;            /* TIMER 3 OVERFLOW FLAG        */
sbit EXF3  = TMR3CN ^ 6;            /* TIMER 3 EXTERNAL FLAG        */
sbit EXEN3 = TMR3CN ^ 3;            /* TIMER 3 EXTERNAL ENABLE FLAG */	
sbit TR3   = TMR3CN ^ 2;            /* TIMER 3 ON/OFF CONTROL       */
sbit CT3   = TMR3CN ^ 1;            /* TIMER 3 COUNTER SELECT       */
sbit CPRL3 = TMR3CN ^ 0;            /* TIMER 3 CAPTURE SELECT       */

/*  TMR4CN  0xC8 */
sbit TF4   = TMR4CN ^ 7;            /* TIMER 4 OVERFLOW FLAG        */
sbit EXF4  = TMR4CN ^ 6;            /* TIMER 4 EXTERNAL FLAG        */
sbit EXEN4 = TMR4CN ^ 3;            /* TIMER 4 EXTERNAL ENABLE FLAG */	
sbit TR4   = TMR4CN ^ 2;            /* TIMER 4 ON/OFF CONTROL       */
sbit CT4   = TMR4CN ^ 1;            /* TIMER 4 COUNTER SELECT       */
sbit CPRL4 = TMR4CN ^ 0;            /* TIMER 4 CAPTURE SELECT       */

/*  PSW 0xD0 */
sbit CY  = PSW ^ 7;                 /* CARRY FLAG              */	
sbit AC  = PSW ^ 6;                 /* AUXILIARY CARRY FLAG    */
sbit F0  = PSW ^ 5;                 /* USER FLAG 0             */
sbit RS1 = PSW ^ 4;                 /* REGISTER BANK SELECT 1  */
sbit RS0 = PSW ^ 3;                 /* REGISTER BANK SELECT 0  */
sbit OV  = PSW ^ 2;                 /* OVERFLOW FLAG           */
sbit F1  = PSW ^ 1;                 /* USER FLAG 1             */
sbit P   = PSW ^ 0;                 /* ACCUMULATOR PARITY FLAG */

/* PCA0CN 0xD8 */
sbit CF   = PCA0CN ^ 7;             /* PCA 0 COUNTER OVERFLOW FLAG   */
sbit CR   = PCA0CN ^ 6;             /* PCA 0 COUNTER RUN CONTROL BIT */
sbit CCF5 = PCA0CN ^ 5;             /* PCA 0 MODULE 5 INTERRUPT FLAG */
sbit CCF4 = PCA0CN ^ 4;             /* PCA 0 MODULE 4 INTERRUPT FLAG */
sbit CCF3 = PCA0CN ^ 3;             /* PCA 0 MODULE 3 INTERRUPT FLAG */
sbit CCF2 = PCA0CN ^ 2;             /* PCA 0 MODULE 2 INTERRUPT FLAG */
sbit CCF1 = PCA0CN ^ 1;             /* PCA 0 MODULE 1 INTERRUPT FLAG */
sbit CCF0 = PCA0CN ^ 0;             /* PCA 0 MODULE 0 INTERRUPT FLAG */


/* ADC0CN 0xE8 */
sbit AD0EN   = ADC0CN ^ 7;          /* ADC 0 ENABLE                   */
sbit AD0TM   = ADC0CN ^ 6;          /* ADC 0 TRACK MODE               */
sbit AD0INT  = ADC0CN ^ 5;          /* ADC 0 EOC INTERRUPT FLAG       */
sbit AD0BUSY = ADC0CN ^ 4;          /* ADC 0 BUSY FLAG                */
sbit AD0CM1  = ADC0CN ^ 3;          /* ADC 0 CONVERT START MODE BIT 1 */
sbit AD0CM0  = ADC0CN ^ 2;          /* ADC 0 CONVERT START MODE BIT 0 */
sbit AD0WINT = ADC0CN ^ 1;          /* ADC 0 WINDOW INTERRUPT FLAG    */


/* ADC2CN 0xE8 */
sbit AD2EN   = ADC2CN ^ 7;          /* ADC 2 ENABLE                   */
sbit AD2TM   = ADC2CN ^ 6;          /* ADC 2 TRACK MODE               */
sbit AD2INT  = ADC2CN ^ 5;          /* ADC 2 EOC INTERRUPT FLAG       */
sbit AD2BUSY = ADC2CN ^ 4;          /* ADC 2 BUSY FLAG                */
sbit AD2WINT = ADC2CN ^ 3;          /* ADC 2 WINDOW INTERRUPT FLAG    */
sbit AD2CM2  = ADC2CN ^ 2;          /* ADC 2 CONVERT START MODE BIT 2 */
sbit AD2CM1  = ADC2CN ^ 1;          /* ADC 2 CONVERT START MODE BIT 1 */
sbit AD2CM0  = ADC2CN ^ 0;          /* ADC 2 CONVERT START MODE BIT 0 */

/* SPI0CN 0xF8 */
sbit SPIF   = SPI0CN ^ 7;           /* SPI 0 INTERRUPT FLAG          */
sbit WCOL   = SPI0CN ^ 6;           /* SPI 0 WRITE COLLISION FLAG    */
sbit MODF   = SPI0CN ^ 5;           /* SPI 0 MODE FAULT FLAG         */
sbit RXOVRN = SPI0CN ^ 4;           /* SPI 0 RX OVERRUN FLAG         */
sbit NSSMD1 = SPI0CN ^ 3;			/* SPI 0 SLAVE SELECT MODE BIT 1 */
sbit NSSMD0 = SPI0CN ^ 2;			/* SPI 0 SLAVE SELECT MODE BIT 0 */
sbit TXBMT  = SPI0CN ^ 1;           /* SPI 0 TX BUFFER EMPTY         */
sbit SPIEN  = SPI0CN ^ 0;           /* SPI 0 SPI ENABLE              */			

/* CAN0CN 0xF8 */
sbit CANINIT = CAN0CN ^ 0;         /* CAN Initialization bit */
sbit CANIE   = CAN0CN ^ 1;         /* CAN Module Interrupt Enable Bit */
sbit CANSIE  = CAN0CN ^ 2;         /* CAN Status change Interrupt Enable Bit */
sbit CANEIE  = CAN0CN ^ 3;         /* CAN Module Error Interrupt Enable Bit */
sbit CANIF   = CAN0CN ^ 4;         /* CAN Module Interrupt Flag */
sbit CANDAR  = CAN0CN ^ 5;         /* CAN Disable Automatic Retransmission bit */
sbit CANCCE  = CAN0CN ^ 6;         /* CAN Configuration Change Enable bit */
sbit CANTEST = CAN0CN ^ 7;         /* CAN Test Mode Enable bit */



/* SFR PAGE DEFINITIONS */
#define  CONFIG_PAGE       0x0F     /* SYSTEM AND PORT CONFIGURATION PAGE */
#define  LEGACY_PAGE       0x00     /* LEGACY SFR PAGE                    */
#define  TIMER01_PAGE      0x00     /* TIMER 0 AND TIMER 1                */
#define  CPT0_PAGE         0x01     /* COMPARATOR 0                       */
#define  CPT1_PAGE         0x02     /* COMPARATOR 1                       */
#define  CPT2_PAGE         0x03     /* COMPARATOR 2                       */
#define  UART0_PAGE        0x00     /* UART 0                             */
#define  UART1_PAGE        0x01     /* UART 1                             */
#define  SPI0_PAGE         0x00     /* SPI 0                              */
#define  EMI0_PAGE         0x00     /* EXTERNAL MEMORY INTERFACE          */
#define  ADC0_PAGE         0x00     /* ADC 0                              */
#define  ADC2_PAGE         0x02     /* ADC 2                              */
#define  SMB0_PAGE         0x00     /* SMBUS 0                            */
#define  TMR2_PAGE         0x00     /* TIMER 2                            */
#define  TMR3_PAGE         0x01     /* TIMER 3                            */
#define  TMR4_PAGE         0x02     /* TIMER 4                            */
#define  DAC0_PAGE         0x00     /* DAC 0                              */
#define  DAC1_PAGE         0x01     /* DAC 1                              */
#define  PCA0_PAGE         0x00     /* PCA 0                              */
#define  CAN0_PAGE         0x01     /* CAN 0                              */