/******************************************************************************
    uC/OS-II Porting for LPC210x

    By: Pary WU <parywu@mail2000.com.tw>
    History:
    0406271325:parywu
        The first stable release.
    0406281914:parywu
        ARM/Thumb interworking okay.      
******************************************************************************/
#ifndef __CONFIG_H_040616175535
#define __CONFIG_H_040616175535
/*******************************************************************************
    User Configuration
*******************************************************************************/
/* hardware */
#define cFOSC         11059200  /* frequency of crystall oscillator */
#define cPLLMUL       1         /* PLL clock multiplier */
#define cPLLDIV       4         /* PLL clock divider */
#define cVPBDIV       2         /* VPB clock divider */
#define cMAMMODE      2         /* MAM Mode, 0=disable, 1=partially, 2=full */
#define cMAMTIM       2         /* MAM TIMING */

#define cU0BAUDRATE   115200
#define cU0LCR        3         /* UART 8-1-n */

#define cTick         100       /* Tick, Hz; shall match OS_TICKS_PER_SEC in os_cfg.h */
#define cUseConsole   1         /* Use UART0 as Console (majorly for debug)? */
#define cDebugMode    0         /* Enable debug functions? */
#define cCThumbMode   1         /* Use ThumbMode in .c files? */

/* vector relatives, shall match as in init.s */
#define SRAM_SIZE_LPC2106   64*1024         /* LPC2106 */
#define SRAM_SIZE_LPC2105   32*1024         /* LPC2105 */
#define SRAM_SIZE_LPC2104   16*1024         /* LPC2104 */
#define SRAM_SIZE           SRAM_SIZE_LPC2104
#define SRAM_BEG_ADDR       0x40000000
#define IRQ_BEG_ADDR        SRAM_BEG_ADDR
#define IRQ_NUM             17

/*******************************************************************************
    Translation to register settings from Configuration
    Automatic calculated, without manually change
*******************************************************************************/
/******************************************************************************
    APPLICATION NOTE FOR CLOCK CALCULATION
    
    Fosc: crystal oscillator
    Fcco: Current Controleld Oscillator
    cclk: processor clock
    pclk: VPB clock (for peripherals)
    vpbdiv: VPB divider
    M: PLL Multiplier from the MSEL bits in the PLLCFG register
    P: PLL Divider value from the PSEL bits in the PLLCFG register
    1. decide Fosc
    2. cclk = M * Fosc
    3. Fcco = 2 * M * P * Fosc and satisfies 156MHz <= Fcco <= 320MHz
    4. P = 1, 2, 4, or 8; M = 1 to 32
    5. M, P must be selected to satisfy item 3 and 4.
    6. pclk = cclk / vpbdiv
******************************************************************************/
#define vFOSC   cFOSC
#define vPLLMUL (cPLLMUL-1)

#if (cPLLDIV == 1)
#define vPLLDIV 0x00
#elif (cPLLDIV == 2)
#define vPLLDIV 0x01
#elif (cPLLDIV == 4)
#define vPLLDIV 0x02
#elif (cPLLDIV == 8)
#define vPLLDIV 0x03
#else
#error cPLLDIV valid values: 1, 2, 4, 8
#endif

#define vPLLCFG ((unsigned char)(vPLLMUL|(vPLLDIV<<5)))

#define vVPBDIV     cVPBDIV
#define vMAMMODE    cMAMMODE
#define vMAMTIM     cMAMTIM

#define vCCLK      (cFOSC*cPLLMUL)      /* processor clock */
#define vPCLK      (vCCLK/cVPBDIV)      /* VPB clock, for peripherals */

/* UART0 */
#define vU0DLM     ((unsigned char)(((vPCLK/16/cU0BAUDRATE)/256))) 
#define vU0DLL     ((unsigned char)(((vPCLK/16/cU0BAUDRATE)%256)))
#define vU0LCR      cU0LCR

/* Timer 0 */
#define vT0PC       0               /* we do not use prescale */
#define vT0MR0      (vPCLK/cTick)
#define vT0MCR      3               /* interrupt and reset timer0 when matches */
#endif /* __CONFIG_H_040616175535 */