module	Reset_Delay(iCLK,oRST);
input		iCLK;
output reg	oRST;
reg	[32:0]	Cont;

always@(posedge iCLK )
begin
		if(Cont==13'hFFF)
		oRST	<=	1;
		else
		Cont<=Cont+1;
end

endmodule