module	memory (	CS,RD,ready,odata,iCLK,trigger	);
input               trigger;
input               CS;
input               RD; 						
input				iCLK;
wire				iRST_N;
output      reg     ready;
output      [7:0]   odata;  
reg         [7:0]   odata;
//	Horizontal Parameter	( Pixel )     Virtical Parameter		( Line )
parameter	H_TOTAL	=	512;
//parameter	V_TOTAL =	1024;
//state??
reg  [5:0] state;
parameter Idle		=5'b00000;
parameter sdRD		=5'b00001;
parameter shRD	    =5'b01000;
parameter sCS		=5'b10000;
//	Internal Registers and Wires
reg		[11:0]		H_Cont;
//reg		[11:0]		V_Cont;
//reg     [ 7:0]      simulate;
//reg                flg;

Reset_Delay			u2	(	.iCLK(iCLK),
							.oRST(iRST_N)	);	
							


always@(posedge iCLK or negedge iRST_N )
begin
	if(! iRST_N)
	  begin
        odata       <= 8'bZZZZZZZZ;
        state       <= Idle; 
 //       flg <=1;
      end
	else
	begin
	    case(state)
	     Idle:begin
	              if (! CS) 
	                     state<=sdRD ;
	              else
	                     state<=Idle;
	          end
	
	     sdRD:begin
	             //if(! RD)
	                begin  
	                   odata<=8'b10101010;
		             //  H_Cont <=	H_Cont+1;
	                   state<=sCS;  //shRD;
	                end
	             // else state<=sdRD;
	          end

	 /*    shRD:  begin 
	             if( RD )
	               begin
		              odata  <= 8'bZZZZZZZZ;
	                  state  <= sCS;
//	                  flg <= ~flg; 
	               end
	              else 
	              state<=shRD;
	             end */
	     sCS:  begin
	             if (CS)
	               begin
			              odata  <= 8'bZZZZZZZZ;  
	                 state<=Idle;
	               end
	             else 
	                 state<=sCS;
               end
	    endcase
	end 
end
/*     
always@(posedge iCLK or negedge iRST_N)
 begin
	if(! iRST_N)
		H_Cont  <=	0;
	else
	 begin
	    ready <= 1;
		if( H_Cont >= H_TOTAL-1 )
		H_Cont	<=	0;	
	end 		
 end
*/
/*
always@(posedge iCLK  or posedge iRST_N)
 begin
	if(iRST_N)
		V_Cont	<=	0;		
	else
	  begin
		if(H_Cont==0)
		begin
			if( V_Cont < V_TOTAL )
			V_Cont	<=	V_Cont+1;
			else
			V_Cont	<=	0;
	    end
      end 
  end
 */
//給數據為FF或者00  
/*
always@(posedge iCLK or posedge iRST_N)
 begin
     ready <= 1;
     case(flg)
       1'b0: simulate<=8'b10101010;
       1'b1: simulate<=8'b10101010;
     endcase  
 end	
	*/
endmodule