/********************************************************
*	declare SFR bits										*
********************************************************/

union byte_def {				/* define byte structure */
	struct {
		char	b0:1;
		char	b1:1;
		char	b2:1;
		char	b3:1;
		char	b4:1;
		char	b5:1;
		char	b6:1;
		char	b7:1;
	} bit;
	char	byte;
};

union word_def {				/* define word structure */
	struct {
		char	b0:1;
		char	b1:1;
		char	b2:1;
		char	b3:1;
		char	b4:1;
		char	b5:1;
		char	b6:1;
		char	b7:1;
		char	b8:1;
		char	b9:1;
		char	b10:1;
		char	b11:1;
		char	b12:1;
		char	b13:1;
		char	b14:1;
		char	b15:1;
 	} bit;
	struct {
		char	low;			/* low  8 bits */
		char	high;			/* high 8 bits */
	} byte;
	unsigned short	word;
};

union dword_def {				/* define long word structure */
	struct {
		char	b0:1;
		char	b1:1;
		char	b2:1;
		char	b3:1;
		char	b4:1;
		char	b5:1;
		char	b6:1;
		char	b7:1;
		char	b8:1;
		char	b9:1;
		char	b10:1;
		char	b11:1;
		char	b12:1;
		char	b13:1;
		char	b14:1;
		char	b15:1;
		char	b16:1;
		char	b17:1;
		char	b18:1;
		char	b19:1;
 	} bit;
 	struct {
		char	low;			/* low  8 bits */
		char	mid;			/* mid  8 bits */
		char	high;			/* high 8 bits */
		char	nc;				/* not used */
	} byte;
	unsigned long	dword;
};

/*------------------------------------------------------
	Processor mode register 0
------------------------------------------------------*/
union byte_def pm0_addr;
#define		pm0		pm0_addr.byte

#define		pm00	pm0_addr.bit.b0		/* Processor mode bit 0 */
#define		pm01	pm0_addr.bit.b1		/* Processor mode bit 1 */
#define		pm02	pm0_addr.bit.b2		/* R/W mode select bit */
#define		pm03	pm0_addr.bit.b3		/* Software reset bit */
#define		pm06	pm0_addr.bit.b6		/* Port P4_0 to P4_3 function select bit */
#define		pm07	pm0_addr.bit.b7		/* BCLK output disable bit */

/*------------------------------------------------------
	Processor mode register 1
------------------------------------------------------*/
union byte_def pm1_addr;
#define		pm1		pm1_addr.byte

#define		pm16	pm1_addr.bit.b6		/* WR length control bit */
#define		pm17	pm1_addr.bit.b7		/* Wait bit */

/*------------------------------------------------------
	System clock control register 0
------------------------------------------------------*/
union byte_def cm0_addr;
#define		cm0		cm0_addr.byte

#define		cm02	cm0_addr.bit.b2		/* Wait peripheral function clock stop bit */
#define		cm03	cm0_addr.bit.b3		/* Xcin-Xcout drive capacity select bit */
#define		cm04	cm0_addr.bit.b4		/* Port Xc select bit */
#define		cm05	cm0_addr.bit.b5		/* Main clock stop bit */
#define		cm06	cm0_addr.bit.b6		/* Main clock division select bit 0 */
#define		cm07	cm0_addr.bit.b7		/* System clock select bit */

/*------------------------------------------------------
	System clock control register 1
------------------------------------------------------*/
union byte_def cm1_addr;
#define		cm1		cm1_addr.byte

#define		cm10	cm1_addr.bit.b0		/* All clock stop control bit */
#define		cm15	cm1_addr.bit.b5		/* Xin-Xout drive capacity select bit */
#define		cm16	cm1_addr.bit.b6		/* Main clock division select bit */
#define		cm17	cm1_addr.bit.b7		/* Main clock division select bit */

/*------------------------------------------------------
	Chip select control register
------------------------------------------------------*/
union byte_def csr_addr;
#define		csr		csr_addr.byte

#define		cs0		csr_addr.bit.b0		/* CS0 output enable bit */
#define		cs1		csr_addr.bit.b1		/* CS1 output enable bit */
#define		cs2		csr_addr.bit.b2		/* CS2 output enable bit */
#define		cs3		csr_addr.bit.b3		/* CS3 output enable bit */
#define		cs0w	csr_addr.bit.b4		/* CS0 wait bit	*/
#define		cs1w	csr_addr.bit.b5		/* CS1 wait bit	*/
#define		cs2w	csr_addr.bit.b6		/* CS2 wait bit	*/
#define		cs3w	csr_addr.bit.b7		/* CS3 wait bit	*/

/*------------------------------------------------------
	Address match interrupt enable register
------------------------------------------------------*/
union byte_def aier_addr;
#define		aier		aier_addr.byte

#define		aier0		aier_addr.bit.b0	/* Addrese match interrupt 0 enable bit */
#define		aier1		aier_addr.bit.b1	/* Addrese match interrupt 1 enable bit */

/*------------------------------------------------------
	Protect register
------------------------------------------------------*/
union byte_def prcr_addr;
#define		prcr		prcr_addr.byte

#define		prc0		prcr_addr.bit.b0	/* Enables writing to system clock control register 0,1 */
#define		prc1		prcr_addr.bit.b1	/* Enables writing to processor mode register 0,1 */
#define		prc2		prcr_addr.bit.b2	/* Enables writing to port 9 direction register  */

/*------------------------------------------------------
	USB control register
------------------------------------------------------*/
union byte_def usbc_addr;
#define		usbc		usbc_addr.byte

#define		usbc5		usbc_addr.bit.b5	/* USB clock enable bit */
#define		usbc6		usbc_addr.bit.b6	/* USB /SOF port select bit */
#define		usbc7		usbc_addr.bit.b7	/* USB Enable bit */

/*------------------------------------------------------
	Watchdog timer start register
------------------------------------------------------*/
union byte_def wdts_addr;
#define		wdts		wdts_addr.byte

/*------------------------------------------------------
	Watchdog timer control register
------------------------------------------------------*/
union byte_def wdc_addr;
#define		wdc		wdc_addr.byte

#define		wdc7		wdc_addr.bit.b7		/* Prescaler select bit */

/*------------------------------------------------------
	Address match interrupt register 0
------------------------------------------------------*/
union 	dword_def	rmad0_addr;
#define		rmad0	rmad0_addr.dword		/* Address match interrupt register0 32 bit */
#define		rmad0l	rmad0_addr.byte.low		/* Address match interrupt register0 low  8 bit */
#define		rmad0m	rmad0_addr.byte.mid    	/* Address match interrupt register0 mid  8 bitt */
#define		rmad0h	rmad0_addr.byte.high   	/* Address match interrupt register0 high 8 bit */

/*------------------------------------------------------
	Address match interrupt register 1
------------------------------------------------------*/
union 	dword_def	rmad1_addr;
#define		rmad1	rmad1_addr.dword		/* Address match interrupt register1 32 bit */
#define		rmad1l	rmad1_addr.byte.low 	/* Address match interrupt register1 low  8 bit */
#define		rmad1m	rmad1_addr.byte.mid     /* Address match interrupt register1 mid  8 bit */
#define		rmad1h	rmad1_addr.byte.high 	/* Address match interrupt register1 high 8 bit */

/*------------------------------------------------------
	Chip select expansion register
------------------------------------------------------*/
union byte_def cse_addr;
#define		cse		cse_addr.byte

#define		cse0w0		cse_addr.bit.b0		/* CS0 wait expansion bit 0 */
#define		cse0w1		cse_addr.bit.b1		/* CS0 wait expansion bit 1 */
#define		cse1w0		cse_addr.bit.b2		/* CS1 wait expansion bit 0 */
#define		cse1w1		cse_addr.bit.b3		/* CS1 wait expansion bit 1 */
#define		cse2w0		cse_addr.bit.b4		/* CS2 wait expansion bit 0 */
#define		cse2w1		cse_addr.bit.b5		/* CS2 wait expansion bit 1 */
#define		cse3w0		cse_addr.bit.b6		/* CS3 wait expansion bit 0 */
#define		cse3w1		cse_addr.bit.b7		/* CS3 wait expansion bit 1 */

/*------------------------------------------------------
	USB attach / detach register
------------------------------------------------------*/
union byte_def usbad_addr;
#define		usbad		usbad_addr.byte

#define		p90_2nd		usbad_addr.bit.b0  	/* PORT90 SECOND */
#define		attach		usbad_addr.bit.b1  	/* Attach/Detach select bit*/
#define		vbdt		usbad_addr.bit.b7  	/* Vbus Detect enable bit*/

/*------------------------------------------------------
	DMA0 source pointer
------------------------------------------------------*/
union dword_def sar0_addr;
#define		sar0	sar0_addr.dword			/* DMA0 source pointer 32 bit */
#define		sar0l	sar0_addr.byte.low		/* DMA0 source pointer low  8 bit */
#define		sar0m	sar0_addr.byte.mid		/* DMA0 source pointer mid  8 bit */
#define		sar0h	sar0_addr.byte.high		/* DMA0 source pointer high 8 bit */

/*------------------------------------------------------
	DMA0 destination pointer
------------------------------------------------------*/
union dword_def dar0_addr;
#define		dar0	dar0_addr.dword			/* DMA0 destination pointer 32 bit */
#define		dar0l	dar0_addr.byte.low     	/* DMA0 destination pointer low  8 bit */
#define		dar0m	dar0_addr.byte.mid     	/* DMA0 destination pointer mid  8 bit */
#define		dar0h	dar0_addr.byte.high    	/* DMA0 destination pointer high 8 bit */

/*------------------------------------------------------
	DMA0 transfer counter
------------------------------------------------------*/
union word_def tcr0_addr;
#define		tcr0	tcr0_addr.word	 		/* DMA0 transfer counter 16 bit */
#define		tcr0l	tcr0_addr.byte.low		/* DMA0 transfer counter low  8 bit */
#define		tcr0h	tcr0_addr.byte.high		/* DMA0 transfer counter high 8 bit */

/*------------------------------------------------------
	 DMA0 control register
------------------------------------------------------*/
union byte_def dm0con_addr;
#define		dm0con			dm0con_addr.byte

#define		dmbit_d0	dm0con_addr.bit.b0	/* Transfer unit bit select bit */
#define		dmasl_d0	dm0con_addr.bit.b1	/* Repeat transfer mode select bit */
#define		dmas_d0		dm0con_addr.bit.b2	/* DMA request bit */