#ifndef __ASM_LANGUAGE__#define __ASM_LANGUAGE__#endif#include "hfrk.h".text/* must be in text segment! */#include "2410addr.inc"/* values for init registers */#define _DISABLE_WDT_VAL       0x00000000#define _DISABLE_INT_VAL       0xffffffff#define _DISABLE_SUBINT_VAL    0x000003ff#define _LOCK_TIME_VAL         0x00ffffff/* 0x5c << 12 + 0x04 << 4 + 0x02 */#define _MPLLCON_DAT_VAL       0x0005c042/* 0 + B1_BWSCON << 4 + B2_BWSCON << 8 + B3_BWSCON << 12 + B4_BWSCON << 16 + B5_BWSCON << 20 + B6_BWSCON << 24 + B7_BWSCON << 28 *//* 1 << 4 + 1 << 8 + 13 << 12 + 1 << 16 + 1 << 20 + 2 << 24 + 2 << 28 */#define _BWSCON_VAL            0x2211d110/* Bn_Tacs << 13 + Bn_Tcos << 11 + Bn_Tacc << 8 + Bn_Tcoh << 6 + Bn_Tah << 4 + Bn_Tacp << 2 + Bn_PMC *//* 3 << 13 + 3 << 11 + 7 << 8 + 3 << 6 + 3 << 4 + 1 << 2 + 0 */#define _BANKCON0_VAL          0x00007ff4/* 3 << 13 + 3 << 11 + 7 << 8 + 3 << 6 + 3 << 4 + 3 << 2 + 0 */#define _BANKCON1_VAL          0x00007ffc/* 0 << 13 + 0 << 11 + 7 << 8 + 0 << 6 + 0 << 4 + 0 << 2 + 0 */#define _BANKCON2_VAL          0x00000700/* 0 << 13 + 3 << 11 + 7 << 8 + 1 << 6 + 3 << 4 + 3 << 2 + 0 */#define _BANKCON3_VAL          0x00001f7c/* 0 << 13 + 0 << 11 + 7 << 8 + 0 << 6 + 0 << 4 + 0 << 2 + 0 */#define _BANKCON4_VAL          0x00000700/* 0 << 13 + 0 << 11 + 7 << 8 + 0 << 6 + 0 << 4 + 0 << 2 + 0 */#define _BANKCON5_VAL          0x00000700/* Bn_MT << 15 + Bn_Trcd << 2 + Bn_SCAN *//* 3 << 15 + 1 << 2 + 1 */#define _BANKCON6_VAL          0x00018005/* 3 << 15 + 1 << 2 + 1 */#define _BANKCON7_VAL          0x00018005/* REFEN << 23 + TREFMD << 22 + Trp << 20 + Trc << 18 + Tchr << 16 + REFCNT *//* 1 << 23 + 0 << 22 + 0 << 20 + 3 << 18 + 2 << 16 + 1113 */#define _REFRESH_VAL           0x008e0459#define _BANKSIZE_VAL          0x00000031#define _MRSRB6_VAL            0x00000030#define _MRSRB7_VAL            0x00000030hfrk_brd_init:    /* save lr and don't change r6 */    mov    r6, lr    /* !!! ATTENTION HERE !!! */    /* enter svc mode and disable irq/fiq */    mrs r2, cpsr     orr r2, r2, #0xc0    msr cpsr_c, r2    /* disable wdt */    ldr    r2, =WTCON    ldr    r3, =_DISABLE_WDT_VAL    str    r3, [r2]    /* disable all interrupts */    ldr    r2, =INTMSK    ldr    r3, =_DISABLE_INT_VAL    str    r3, [r2]    /* disable all sub-interrputs */    ldr    r2, =INTSUBMSK    ldr    r3, =_DISABLE_SUBINT_VAL    str    r3, [r2]    /* adjust PLL lock time */    ldr    r2, =LOCKTIME    ldr    r3, =_LOCK_TIME_VAL    str    r3, [r2]    /* config PLL */    ldr    r2, =MPLLCON    ldr    r3, =_MPLLCON_DAT_VAL    str    r3, [r2]    /* init memory control register */    ldr    r2, =BWSCON    /* bwscon */    ldr    r3, =_BWSCON_VAL    str    r3, [r2]    /* bank0 */    ldr    r2, =BANKCON0    ldr    r3, =_BANKCON0_VAL    str    r3, [r2]    /* bank1 */    ldr    r2, =BANKCON1    ldr    r3, =_BANKCON1_VAL    str    r3, [r2]    /* bank2 */    ldr    r2, =BANKCON2    ldr    r3, =_BANKCON2_VAL    str    r3, [r2]    /* bank3 */    ldr    r2, =BANKCON3    ldr    r3, =_BANKCON3_VAL    str    r3, [r2]    /* bank4 */    ldr    r2, =BANKCON4    ldr    r3, =_BANKCON4_VAL    str    r3, [r2]    /* bank5 */    ldr    r2, =BANKCON5    ldr    r3, =_BANKCON5_VAL    str    r3, [r2]    /* bank6 */    ldr    r2, =BANKCON6    ldr    r3, =_BANKCON6_VAL    str    r3, [r2]    /* bank7 */    ldr    r2, =BANKCON7    ldr    r3, =_BANKCON7_VAL    str    r3, [r2]    /* refresh */    ldr    r2, =REFRESH    ldr    r3, =_REFRESH_VAL    str    r3, [r2]    /* bank size */    ldr    r2, =BANKSIZE    ldr    r3, =_BANKSIZE_VAL    str    r3, [r2]    /* mrsrb6 */    ldr    r2, =MRSRB6    ldr    r3, =_MRSRB6_VAL    str    r3, [r2]    /* mrsrb7 */    ldr    r2, =MRSRB7    ldr    r3, =_MRSRB7_VAL    str    r3, [r2]    mov    pc, r6/*****************************************************************************//* Pre-defined constants */#define USERMODE         0x10#define FIQMODE          0x11#define IRQMODE          0x12#define SVCMODE          0x13#define ABORTMODE        0x17#define UNDEFMODE        0x1b#define MODEMASK         0x1f#define NOINT            0xc0                                                                                                                             /* The location of stacks */_UserStack:   .word (STACK_BASE_ADDR - 0x3800) /* 0x33ff4800 ~ */_SVCStack:    .word (STACK_BASE_ADDR - 0x2800) /* 0x33ff5800 ~ */_UndefStack:  .word (STACK_BASE_ADDR - 0x2400) /* 0x33ff5c00 ~ */_AbortStack:  .word (STACK_BASE_ADDR - 0x2000) /* 0x33ff6000 ~ */_IRQStack:    .word (STACK_BASE_ADDR - 0x1000) /* 0x33ff7000 ~ */_FIQStack:    .word (STACK_BASE_ADDR - 0x0)    /* 0x33ff8000 ~ */hfrk_init_stack:    /* Don't use DRAM, such as stmfd,ldmfd...... */    /* SVCstack is initialized before */    /* Under toolkit ver 2.5, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1' */    mrs r0, cpsr    bic r0, r0, #MODEMASK    orr r1, r0, #UNDEFMODE|NOINT    msr cpsr_cxsf, r1        /* UndefMode */    ldr sp, _UndefStack    orr r1, r0, #ABORTMODE|NOINT    msr cpsr_cxsf, r1        /* AbortMode */    ldr sp, _AbortStack    orr r1, r0, #IRQMODE|NOINT    msr cpsr_cxsf, r1        /* IRQMode */    ldr sp, _IRQStack    orr r1, r0, #FIQMODE|NOINT    msr cpsr_cxsf, r1        /* FIQMode */    ldr sp, _FIQStack    bic r0, r0, #MODEMASK|NOINT    orr r1, r0, #SVCMODE    msr cpsr_cxsf, r1        /* SVCMode */    ldr sp, _SVCStack    /* USER mode has not be initialized. */    mov pc,lr    /* The LR register won't be valid if the current mode is not SVC mode. *//*****************************************************************************/#define _GPF_CON_0_VAL         0x00005500#define _GPF_DAT_0_VAL         0x00000010led_on:    ldr    r2, =GPFCON    ldr    r3, =_GPF_CON_0_VAL    str    r3, [r2]    ldr    r2, =GPFDAT    ldr    r3, =_GPF_DAT_0_VAL    str    r3, [r2]    mov    pc, lr/*****************************************************************************/hfrk_create_core_param:    ldr    r2, =GSTATUS2    ldr    r0, [r2] /* r0 is the return register */    cmp    r0, #0x00 /* if zero, it means the soft reset */    ldreq  r0, =SOFT_RESET_FLAG    strne  r0, [r2] /* clear reset status */    mov    pc, lr