?? test.c.bak
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#define CHIP_DM642 1#define OV7640_R_ADDRESS 0x43#define OV7640_W_ADDRESS 0x42#include <csl.h>#include <csl_i2c.h>#include <csl_emifa.h>#include <stdio.h>CHIP_Config chippercfg = { CHIP_I2C+CHIP_VP1,};EMIFA_Config emifaCfg0 = {// EMIFA_FMKS(GBLCTL, EK2RATE, HALFCLK) |// EMIFA_FMKS(GBLCTL, EK2HZ, CLK) |// EMIFA_FMKS(GBLCTL, EK2EN, ENABLE) | EMIFA_FMKS(GBLCTL, BRMODE, MRSTATUS) | EMIFA_FMKS(GBLCTL, NOHOLD, DISABLE) | EMIFA_FMKS(GBLCTL, EK1HZ, HIGHZ) | EMIFA_FMKS(GBLCTL, EK1EN, ENABLE),// EMIFA_FMKS(GBLCTL, CLK4EN, ENABLE) |// EMIFA_FMKS(GBLCTL, CLK6EN, ENABLE), EMIFA_FMKS(CECTL, WRSETUP, DEFAULT) | EMIFA_FMKS(CECTL, WRSTRB, DEFAULT) | EMIFA_FMKS(CECTL, WRHLD, DEFAULT) | EMIFA_FMKS(CECTL, RDSETUP, DEFAULT) | EMIFA_FMKS(CECTL, TA, DEFAULT) | EMIFA_FMKS(CECTL, RDSTRB, DEFAULT) | EMIFA_FMKS(CECTL, MTYPE, SDRAM64) | EMIFA_FMKS(CECTL, RDHLD, DEFAULT), EMIFA_FMKS(CECTL, WRSETUP, OF(7)) | EMIFA_FMKS(CECTL, WRSTRB, OF(14)) | EMIFA_FMKS(CECTL, WRHLD, OF(2)) | EMIFA_FMKS(CECTL, RDSETUP, OF(2)) | EMIFA_FMKS(CECTL, TA, OF(2)) | EMIFA_FMKS(CECTL, RDSTRB, OF(14)) | EMIFA_FMKS(CECTL, MTYPE, ASYNC8) | EMIFA_FMKS(CECTL, RDHLD, OF(1)), EMIFA_CECTL_DEFAULT, EMIFA_CECTL_DEFAULT, EMIFA_FMKS(SDCTL, SDBSZ, 4BANKS) | EMIFA_FMKS(SDCTL, SDRSZ, 12ROW) | EMIFA_FMKS(SDCTL, SDCSZ, 8COL) | EMIFA_FMKS(SDCTL, RFEN, ENABLE) | EMIFA_FMKS(SDCTL, INIT, YES) | EMIFA_FMKS(SDCTL, TRCD, OF(1)) | EMIFA_FMKS(SDCTL, TRP, OF(1)) | EMIFA_FMKS(SDCTL, TRC, OF(5)) | EMIFA_FMKS(SDCTL, SLFRFR, DISABLE), EMIFA_FMKS(SDTIM, XRFR, OF(0)) | EMIFA_FMKS(SDTIM, PERIOD, OF(2075)), EMIFA_FMKS(SDEXT, WR2RD, OF(1)) | EMIFA_FMKS(SDEXT, WR2DEAC, OF(3)) | EMIFA_FMKS(SDEXT, WR2WR, OF(1)) | EMIFA_FMKS(SDEXT, R2WDQM, OF(3)) | EMIFA_FMKS(SDEXT, RD2WR, OF(2)) | EMIFA_FMKS(SDEXT, RD2DEAC, OF(3)) | EMIFA_FMKS(SDEXT, RD2RD, OF(1)) | EMIFA_FMKS(SDEXT, THZP, OF(2)) | EMIFA_FMKS(SDEXT, TWR, OF(2)) | EMIFA_FMKS(SDEXT, TRRD, OF(0)) | EMIFA_FMKS(SDEXT, TRAS, OF(6)) | EMIFA_FMKS(SDEXT, TCL, OF(1)), EMIFA_CESEC_DEFAULT, EMIFA_CESEC_DEFAULT, EMIFA_CESEC_DEFAULT, EMIFA_CESEC_DEFAULT, };// I2C_Config i2cCfg = {// 0x00000000, /* I2COAR - Not used if master */// 0x00000000, /* I2CIER - Disable interrupts, use polling */// 0x00000014, /* I2CCLKL - Low period for 200KHz operation */// 0x00000014, /* I2CCLKH - High period for 200KHz operation */// 0x00000000, /* I2CCNT - Data words per transmission */// 0x00000000, /* I2CSAR - Slave address */// 0x00004680, /* I2CMDR - Mode */// 0x0000000D /* I2CPSC - Prescale 150MHz to 10MHz */// }; I2C_Handle g_I2C_Handle; // I2C 全局句柄void Delay(Uint8 nClk){ Uint8 loop; for (loop=nClk;loop==1;loop--){}}Bool I2C_Initialize(void){ g_I2C_Handle = I2C_open(I2C_PORT0,I2C_OPEN_RESET); if(g_I2C_Handle == INV) { return FALSE; } else { I2C_RSETH(g_I2C_Handle, I2CPSC, 0x0D); // I2C模塊時鐘設置為10M 150M/15 I2C_RSETH(g_I2C_Handle, I2CCLKL, 0x14); // 設置I2C外部時鐘為100K I2C_RSETH(g_I2C_Handle, I2CCLKH, 0x14); // 設置I2C外部時鐘為100K return TRUE; }}Uint8 I2C_Write(Uint8 dev_addr, Uint8 *sub_addr, Uint8 sub_addr_len, Uint8 *write_buffer, Uint8 write_len){ Uint8 bResult = 0; Uint32 I2CState;// I2C_Config prevI2CCfg; while (I2C_bb(g_I2C_Handle));// I2C_getConfig(g_I2C_Handle, &prevI2CCfg); // clear all interrupt state I2C_FSETH(g_I2C_Handle, I2CSTR, AL, 1); I2C_FSETH(g_I2C_Handle, I2CSTR, NACK, 1); I2C_FSETH(g_I2C_Handle, I2CSTR, ARDY, 1); I2C_FSETH(g_I2C_Handle, I2CSTR, ICRRDY, 1); I2C_FSETH(g_I2C_Handle, I2CSTR, ICXRDY, 1); // I2C_RSETH(g_I2C_Handle, I2COAR, 0); // I2C_RSETH(g_I2C_Handle, I2CIER, 0); // I2C_RSETH(g_I2C_Handle, I2CCNT, 0); I2C_RSETH(g_I2C_Handle, I2CSAR, dev_addr); // I2C_RSETH(g_I2C_Handle, I2CMDR, 0x26A0); // wait send start condition while(I2C_FGETH(g_I2C_Handle, I2CMDR, STT)); while(1) { I2CState = I2C_RGETH(g_I2C_Handle, I2CSTR); if(I2CState & 0x01) { // Arbitration lost // clear AL state in I2C Status Register I2C_FSETH(g_I2C_Handle, I2CSTR, AL, 1); break; } if(I2CState & 0x04) { // ARDY == 1 if(I2CState & 0x02) { // NACK == 1 // clear NACK state in I2C Status Register I2C_FSETH(g_I2C_Handle, I2CSTR, NACK, 1); break; } else { if(I2CState & 0x10) { // ICXRDY == 1 if(bResult < sub_addr_len)//寫入的字節數小于子地址的長度 { I2C_RSETH(g_I2C_Handle, I2CDXR, sub_addr[bResult]);//傳輸子地址 bResult ++; } else if(bResult < sub_addr_len + write_len)//寫入的字節數小于子地址的長度加數據字節數 { I2C_RSETH(g_I2C_Handle, I2CDXR, write_buffer[bResult - sub_addr_len]); //傳輸數據 bResult ++; } else { break; } } } } } I2C_sendStop(g_I2C_Handle); //I2C_FSETSH(g_I2C_Handle,I2CMDR,STP,STOP); while (I2C_bb(g_I2C_Handle)); // I2C_config(g_I2C_Handle, &prevI2CCfg); return (bResult < sub_addr_len) ? 0 : (bResult - sub_addr_len);}Uint8 I2C_Read(Uint8 dev_addr, Uint8 *sub_addr, Uint8 sub_addr_len, Uint8 *read_buffer, Uint8 read_len){ Uint8 bResult = 0; Uint32 I2CState;// I2C_Config prevI2CCfg; if(read_len == 0) { return 0; } while (I2C_bb(g_I2C_Handle)); // I2C_getConfig(g_I2C_Handle, &prevI2CCfg); // clear all interrupt state I2C_FSETH(g_I2C_Handle, I2CSTR, AL, 1); I2C_FSETH(g_I2C_Handle, I2CSTR, NACK, 1); I2C_FSETH(g_I2C_Handle, I2CSTR, ARDY, 1); I2C_FSETH(g_I2C_Handle, I2CSTR, ICRRDY, 1); I2C_FSETH(g_I2C_Handle, I2CSTR, ICXRDY, 1); // 寫子地址 if(sub_addr_len) { I2C_RSETH(g_I2C_Handle, I2CCNT, 1+read_len);//設置要讀取的長度 I2C_RSETH(g_I2C_Handle, I2CSAR, dev_addr); //設置slave的地址 I2C_RSETH(g_I2C_Handle, I2CMDR, I2C_FMKS(I2CMDR, NACKMOD, ACK)| I2C_FMKS(I2CMDR, FREE, BSTOP)| I2C_FMKS(I2CMDR, STT, NONE)| I2C_FMKS(I2CMDR, STP, NONE)| I2C_FMKS(I2CMDR, MST, MASTER)| //Master mode I2C_FMKS(I2CMDR, TRX, XMT)| //Transmitter mode I2C_FMKS(I2CMDR, XA, 7BIT)| I2C_FMKS(I2CMDR, RM, NONE)| //Nonrepeat mode I2C_FMKS(I2CMDR, DLB, NONE)| I2C_FMKS(I2CMDR, IRS, NRST)| I2C_FMKS(I2CMDR, STB, NONE)| I2C_FMKS(I2CMDR, FDF, NONE)| I2C_FMKS(I2CMDR, BC, BIT8FDF)); // wait send start condition while(I2C_FGETH(g_I2C_Handle, I2CMDR, STT)); while(1) { I2CState = I2C_RGETH(g_I2C_Handle, I2CSTR); if(I2CState & 0x01) { // Arbitration lost I2C_FSETH(g_I2C_Handle, I2CSTR, AL, 1); I2C_sendStop(g_I2C_Handle); //I2C_FSETSH(g_I2C_Handle,I2CMDR,STP,STOP); while (I2C_bb(g_I2C_Handle)); // I2C_config(g_I2C_Handle, &prevI2CCfg); return 0; } if(I2CState & 0x04) { // ARDY == 1 if(I2CState & 0x02) { // NACK == 1 I2C_FSETH(g_I2C_Handle, I2CSTR, NACK, 1); I2C_sendStop(g_I2C_Handle); //I2C_FSETSH(g_I2C_Handle,I2CMDR,STP,STOP); while (I2C_bb(g_I2C_Handle)); // I2C_config(g_I2C_Handle, &prevI2CCfg); return 0; } else { if(I2CState & 0x10) { // ICXRDY == 1 if(bResult < sub_addr_len) { I2C_RSETH(g_I2C_Handle, I2CDXR, sub_addr[bResult]); bResult ++; } else { break; } } } } } } // 是否需要等待由發送轉換為接收 重復起始條件 bResult = 0; I2C_RSETH(g_I2C_Handle, I2COAR, 0); I2C_RSETH(g_I2C_Handle, I2CIER, 0); I2C_RSETH(g_I2C_Handle, I2CCNT, 0); I2C_RSETH(g_I2C_Handle, I2CSAR, dev_addr); I2C_RSETH(g_I2C_Handle, I2CMDR, 0x24A0); // wait send start condition while(I2C_FGETH(g_I2C_Handle, I2CMDR, STT)); while(1) { I2CState = I2C_RGETH(g_I2C_Handle, I2CSTR); if(I2CState & 0x01) { // Arbitration lost I2C_FSETH(g_I2C_Handle, I2CSTR, AL, 1); break; } if(I2CState & 0x04) { // ARDY == 1 if(I2CState & 0x02) { // NACK == 1 I2C_FSETH(g_I2C_Handle, I2CSTR, NACK, 1); break; } else if(I2CState & 0x2000) { // NACKSNT == 1 I2C_FSETH(g_I2C_Handle, I2CSTR, NACKSNT, 1); break; } else { if(I2CState & 0x08) { // ICRRDY == 1 if(bResult < read_len) { read_buffer[bResult] = I2C_RGETH(g_I2C_Handle, I2CDRR); bResult ++; if(bResult >= read_len) { // 如果收完所有字節 則發送NACK I2C_FSETSH(g_I2C_Handle,I2CMDR,NACKMOD,NACK); } } else { I2C_FSETSH(g_I2C_Handle,I2CMDR,NACKMOD,NACK); I2C_RGETH(g_I2C_Handle, I2CDRR); } } } } } I2C_sendStop(g_I2C_Handle); //I2C_FSETSH(g_I2C_Handle,I2CMDR,STP,STOP); while (I2C_bb(g_I2C_Handle)); // I2C_config(g_I2C_Handle, &prevI2CCfg); return bResult;}void main(){// Uint32 gie; Uint8 Result; // Uint8 dev_write_addr=0x42;// Uint8 dev_read_addr=0x43; Uint8 sub_addr[]={0x0A}; Uint8 sub_addr_len=1; Uint8 *read_buffer=(Uint8 *)(0x10000); Uint8 read_len=2; CSL_init();// IRQ_globalDisable(); CHIP_config(&chippercfg); Delay(128); EMIFA_config(&emifaCfg0); I2C_Initialize(); I2C_outOfReset(g_I2C_Handle); // 允許I2C總線 Result = I2C_Read(OV7640_R_ADDRESS,sub_addr,sub_addr_len,read_buffer,read_len);} ?? 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