#ifndef _68VZ328_H_/* * Register definitions for MC68VZ328 Integrated Processor *//* I/O registers base address */#define VZ328IOREGBASE	(0xFFFFF000)/* SIM28 System Configuration Registers */#define	SCR		(VZ328IOREGBASE+0x0000)	/* System control register */#define PCR		(VZ328IOREGBASE+0x0003)	/* Peripheral control register */#define IDR		(VZ328IOREGBASE+0x0004)	/* Silicon ID register */#define IODCR		(VZ328IOREGBASE+0x0008)	/* I/O drive control register *//* Chip Select Registers */#define CSGBA 		(VZ328IOREGBASE+0x0100)	/* Chip-select group A base register */#define CSGBB		(VZ328IOREGBASE+0x0102)	/* Chip-select group B base register */#define CSGBC		(VZ328IOREGBASE+0x0104)	/* Chip-select group C base register */#define CSGBD		(VZ328IOREGBASE+0x0106)	/* Chip-select group D base register */#define	CSUGBA		(VZ328IOREGBASE+0x0108)	/* Chip-select upper group address register */#define	CSCTRL1		(VZ328IOREGBASE+0x010A)	/* Chip-select control register 1 */#define	CSCTRL2		(VZ328IOREGBASE+0x010C)	/* Chip-select control register 2 */#define	CSCTRL3		(VZ328IOREGBASE+0x0150)	/* Chip-select control register 3 */#define CSA		(VZ328IOREGBASE+0x0110)	/* Group A chip-select register */#define CSB		(VZ328IOREGBASE+0x0112)	/* Group B chip-select register */#define CSC		(VZ328IOREGBASE+0x0114)	/* Group C chip-select register */#define CSD		(VZ328IOREGBASE+0x0116)	/* Group D chip-select register *//* Emulator registers */#define EMUCS		(VZ328IOREGBASE+0x0118)	/* Emulation chip-select register *//* PLL Registers */#define PLLCR		(VZ328IOREGBASE+0x0200)	/* Control register */#define PLLFSR		(VZ328IOREGBASE+0x0202)	/* Freq Select register *//* Power Control Registers */#define PCTLR		(VZ328IOREGBASE+0x0207)	/* Control register  *//* Interrupt Registers */#define IVR		(VZ328IOREGBASE+0x0300)	/* Interrupt Vector register */#define ICR		(VZ328IOREGBASE+0x0302)	/* Interrupt Control register */#define IMR		(VZ328IOREGBASE+0x0304)	/* Interrupt Mask register */#define ISR		(VZ328IOREGBASE+0x030C)	/* Interrupt Status register */#define IPR		(VZ328IOREGBASE+0x0310)	/* Interrupt Pending register */#define ILCR		(VZ328IOREGBASE+0x0314)	/* Interrupt level control register *//* Port A Registers */#define PADIR		(VZ328IOREGBASE+0x0400)	/* Port A Direction register */#define PADATA		(VZ328IOREGBASE+0x0401)	/* Port A Data register */#define PAPUEN		(VZ328IOREGBASE+0x0402)	/* Port A Pullup Enable register *//* Port B Registers */#define PBDIR		(VZ328IOREGBASE+0x0408)	/* Port B Direction register */#define PBDATA		(VZ328IOREGBASE+0x0409)	/* Port B Data register */#define PBPUEN		(VZ328IOREGBASE+0x040A)	/* Port B Pullup Enable register */#define PBSEL		(VZ328IOREGBASE+0x040B)	/* Port B Select register *//* Port C Registers  */#define PCDIR		(VZ328IOREGBASE+0x0410)	/* Port C Direction register */#define PCDATA		(VZ328IOREGBASE+0x0411)	/* Port C Data register */#define PCPDEN		(VZ328IOREGBASE+0x0412)	/* Port C Pull-down Enable register */#define PCSEL		(VZ328IOREGBASE+0x0413)	/* Port C Select register *//* Port D Registers */#define PDDIR		(VZ328IOREGBASE+0x0418)	/* Port D Direction register */#define PDDATA		(VZ328IOREGBASE+0x0419)	/* Port D Data register  */#define PDPUEN		(VZ328IOREGBASE+0x041A)	/* Port D Pullup Enable register */#define PDSEL		(VZ328IOREGBASE+0x041B)	/* Port D select */#define PDPOL		(VZ328IOREGBASE+0x041C)	/* Port D Polarity register */#define PDIRQEN		(VZ328IOREGBASE+0x041D)	/* Port D IRQ Enable register */#define PDKBEN		(VZ328IOREGBASE+0x041E)	/* Port D keyboard enable register */#define PDIRQEG		(VZ328IOREGBASE+0x041F)	/* Port D interrupt request edge register *//* Port E Registers */#define PEDIR		(VZ328IOREGBASE+0x0420)	/* Port E Direction register */#define PEDATA		(VZ328IOREGBASE+0x0421)	/* Port E Data register */#define PEPUEN		(VZ328IOREGBASE+0x0422)	/* Port E Pullup Enable register */#define PESEL		(VZ328IOREGBASE+0x0423)	/* Port E Select register *//* Port F Registers */#define PFDIR		(VZ328IOREGBASE+0x0428)	/* Port F Direction register */#define PFDATA		(VZ328IOREGBASE+0x0429)	/* Port F Data register */#define PFPUEN		(VZ328IOREGBASE+0x042A)	/* Port F Pullup Enable register */#define PFSEL		(VZ328IOREGBASE+0x042B)	/* Port F Select register *//* Port G Registers */#define PGDIR		(VZ328IOREGBASE+0x0430)	/* Port G Direction register */#define PGDATA		(VZ328IOREGBASE+0x0431)	/* Port G Data register */#define PGPUEN		(VZ328IOREGBASE+0x0432)	/* Port G Pullup Enable register */#define PGSEL		(VZ328IOREGBASE+0x0433)	/* Port G Select register *//* Port J Registers */#define PJDIR		(VZ328IOREGBASE+0x0438)	/* Port J direction register */#define PJDATA		(VZ328IOREGBASE+0x0439)	/* Port J data register */#define PJPUEN		(VZ328IOREGBASE+0x043A)	/* Port J pull-up enable register */#define PJSEL		(VZ328IOREGBASE+0x043B)	/* Port J select register *//* Port K Registers */#define PKDIR		(VZ328IOREGBASE+0x0440)	/* Port K direction register */#define PKDATA		(VZ328IOREGBASE+0x0441)	/* Port K data register */#define PKPUEN		(VZ328IOREGBASE+0x0442)	/* Port K pull-up/pull-down enable register */#define PKSEL		(VZ328IOREGBASE+0x0443)	/* Port K select register *//* Port M Registers */#define PMDIR		(VZ328IOREGBASE+0x0448)	/* Port M direction register */#define PMDATA		(VZ328IOREGBASE+0x0449)	/* Port M data register */#define PMPUEN		(VZ328IOREGBASE+0x044A)	/* Port M pull-up/pull-down enable register */#define PMSEL		(VZ328IOREGBASE+0x044B)	/* Port M select register *//* PWM unit 1 Registers */#define PWMC1		(VZ328IOREGBASE+0x0500)	/* PWM unit 1 control register */#define PWMS1		(VZ328IOREGBASE+0x0502)	/* PWM unit 1 sample register */#define PWMP1		(VZ328IOREGBASE+0x0504)	/* PWM unit 1 period register */#define PWMCNT1		(VZ328IOREGBASE+0x0505)	/* PWM unit 1 counter register *//* PWM unit 2 Registers */#define PWMC2		(VZ328IOREGBASE+0x0510)	/* PWM unit 2 control register */#define PWMP2		(VZ328IOREGBASE+0x0512)	/* PWM unit 2 period register */#define PWMW2		(VZ328IOREGBASE+0x0514)	/* PWM unit 2 width register */#define PWMCNT2		(VZ328IOREGBASE+0x0516)	/* PWM unit 2 counter register *//* Timer 1 Registers */#define TCTL1		(VZ328IOREGBASE+0x0600)	/* Timer 1 Control register */#define TPRER1		(VZ328IOREGBASE+0x0602)	/* Timer 1 Prescalar register */#define TCMP1		(VZ328IOREGBASE+0x0604)	/* Timer 1 Compare register */#define TCR1		(VZ328IOREGBASE+0x0606)	/* Timer 1 Capture register */#define TCN1		(VZ328IOREGBASE+0x0608)	/* Timer 1 Counter register */#define TSTAT1		(VZ328IOREGBASE+0x060A)	/* Timer 1 Status register *//* Timer 2 Registers */#define TCTL2		(VZ328IOREGBASE+0x0610)	/* Timer 2 Control register */#define TPRER2		(VZ328IOREGBASE+0x0612)	/* Timer 2 Prescalar register */#define TCMP2		(VZ328IOREGBASE+0x0614)	/* Timer 2 Compare register */#define TCR2		(VZ328IOREGBASE+0x0616)	/* Timer 2 Capture register */#define TCN2		(VZ328IOREGBASE+0x0618)	/* Timer 2 Counter register */#define TSTAT2		(VZ328IOREGBASE+0x061A)	/* Timer 2 Status register *//* SPI 1 Registers */#define SPIRXD		(VZ328IOREGBASE+0x0700)	/* Receive data register */#define SPITXD		(VZ328IOREGBASE+0x0702)	/* Transmit data register */#define SPICONT1	(VZ328IOREGBASE+0x0704)	/* Control/status register */#define SPIINTCS	(VZ328IOREGBASE+0x0706)	/* Interrupt control/status register */#define SPITEST		(VZ328IOREGBASE+0x0708)	/* Test register */#define SPISPC		(VZ328IOREGBASE+0x070A)	/* Sample period control register *//* SPI 2 registers */#define SPIDATA2	(VZ328IOREGBASE+0x0800)	/* Control/Status register */#define SPICONT2	(VZ328IOREGBASE+0x0802)	/* Data register *//* UART 1 Registers */#define USTCNT1		(VZ328IOREGBASE+0x0900)	/* Status Control register */#define UBAUD1		(VZ328IOREGBASE+0x0902)	/* Baud Control register */#define URX1		(VZ328IOREGBASE+0x0904)	/* Receive data register */#define UTX1		(VZ328IOREGBASE+0x0906)	/* Transmit data register */#define UMISC1		(VZ328IOREGBASE+0x0908)	/* Miscellaneous register */#define NIPR1		(VZ328IOREGBASE+0x090A)	/* Non-integer prescaler *//* UART 2 Registers */#define USTCNT2		(VZ328IOREGBASE+0x0910)	/* Status/Control register */#define UBAUD2		(VZ328IOREGBASE+0x0912)	/* Baud control register */#define URX2		(VZ328IOREGBASE+0x0914)	/* Receiver data register */#define UTX2		(VZ328IOREGBASE+0x0916)	/* Transmitter data register */#define UMISC2		(VZ328IOREGBASE+0x0918)	/* Miscellaneous register */#define NIPR2		(VZ328IOREGBASE+0x091A)	/* Non-integer prescaler */#define HMARK		(VZ328IOREGBASE+0x091C)	/* FIFO half mark register *//* LCDC Registers */#define LSSA		(VZ328IOREGBASE+0x0A00)	/* Screen Start Addr register */#define LVPW		(VZ328IOREGBASE+0x0A05)	/* Virtual Page Width register */#define LXMAX		(VZ328IOREGBASE+0x0A08)	/* Screen Width register */#define LYMAX		(VZ328IOREGBASE+0x0A0A)	/* Screen Height register */#define LCXP		(VZ328IOREGBASE+0x0A18)	/* Cursor X Position */#define LCYP		(VZ328IOREGBASE+0x0A1A)	/* Cursor Y Position */#define LCWCH		(VZ328IOREGBASE+0x0A1C)	/* Cursor Width & Height register */#define LBLKC		(VZ328IOREGBASE+0x0A1F)	/* Blink Control register */#define LPICF		(VZ328IOREGBASE+0x0A20)	/* Panel Interface Config register */#define LPOLCF		(VZ328IOREGBASE+0x0A21)	/* Polarity Config register */#define LACDRC		(VZ328IOREGBASE+0x0A23)	/* ACD (M) Rate Control register */#define LPXCD		(VZ328IOREGBASE+0x0A25)	/* Pixel Clock Divider register */#define LCKCON		(VZ328IOREGBASE+0x0A27)	/* Clocking Control register */#define LRRA		(VZ328IOREGBASE+0x0A28)	/* Refresh Rate Adjust register */#define LPOSR		(VZ328IOREGBASE+0x0A2D)	/* Panning Offset register */#define LFRCM		(VZ328IOREGBASE+0x0A31)	/* Frame Rate Control Mod register */#define LGPMR		(VZ328IOREGBASE+0x0A33)	/* Gray Palette Mapping register */#define PWMR		(VZ328IOREGBASE+0x0A36)	/* contrast control register */#define RMCR		(VZ328IOREGBASE+0x0A38)	/* Refresh mode control register */#define DMACR		(VZ328IOREGBASE+0x0A39)	/* DMA control register *//* RTC Registers */#define RTCTIME		(VZ328IOREGBASE+0x0B00)	/* RTC time of day register */#define RTCALRM		(VZ328IOREGBASE+0x0B04)	/* RTC Alarm register */#define WATCHDOG	(VZ328IOREGBASE+0x0B0A)	/* RTC watch dog timer register */#define RTCCTL		(VZ328IOREGBASE+0x0B0C)	/* RTC Control register */#define RTCISR		(VZ328IOREGBASE+0x0B0E)	/* RTC Interrupt Status register */#define RTCIENR		(VZ328IOREGBASE+0x0B10)	/* RTC interrupt Enable register */#define STPWCH		(VZ328IOREGBASE+0x0B12)	/* Stopwatch Minutes register *//* DRAM and SDRAM control registers */#define DRAMMC		(VZ328IOREGBASE+0x0C00)	/* DRAM memory configuration register */#define DRAMC		(VZ328IOREGBASE+0x0C02)	/* DRAM control register */#define SDCTRL		(VZ328IOREGBASE+0x0C04)	/* SDRAM control register */#define SDPWDN		(VZ328IOREGBASE+0x0C06)	/* SDRAM power down register *//* ICEM registers */#define ICEMACR		(VZ328IOREGBASE+0x0D00)	/* ICEM address compare register */#define ICEMAMR		(VZ328IOREGBASE+0x0D04)	/* ICEM address mask register */#define ICEMCCR		(VZ328IOREGBASE+0x0D08)	/* ICEM control compare register */#define ICEMCMR		(VZ328IOREGBASE+0x0D0A)	/* ICEM control mask register */#define ICEMCR		(VZ328IOREGBASE+0x0D0C)	/* ICEM control register */#define ICEMSR		(VZ328IOREGBASE+0x0D0E)	/* ICEM status register *//* Enable, Disable and Poll specific Interrupt sources */#define MSPI2	(0x00000001)#define MTMR1	(0x00000002)#define MUART1	(0x00000004)#define MWDT	(0x00000008)#define MRTC	(0x00000010)#define MTMR2	(0x00000020)#define MKB	(0x00000040)#define MPWM1	(0x00000080)#define MINT0	(0x00000100)#define MINT1	(0x00000200)#define MINT2	(0x00000400)#define MINT3	(0x00000800)#define MUART2	(0x00001000)#define MPWM2	(0x00002000)#define MIRQ1	(0x00010000)#define MIRQ2	(0x00020000)#define MIRQ3	(0x00040000)#define MIRQ6	(0x00080000)#define MIRQ5	(0x00100000)#define MSPI1	(0x00200000)#define MRTI	(0x00400000)#endif /* _68VZ328_H_ */