?? ledwater.merge.rpt
字號:
Partition Merge report for ledwater
Tue Aug 28 20:40:19 2007
Quartus II Version 7.0 Build 33 02/05/2007 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Partition Merge Summary
3. Partition Merge Netlist Types Used
4. Partition Merge Partition Statistics
5. Partition Merge Resource Usage Summary
6. Partition Merge Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------+
; Partition Merge Summary ;
+------------------------+-----------------------------------------+
; Partition Merge Status ; Successful - Tue Aug 28 20:40:19 2007 ;
; Quartus II Version ; 7.0 Build 33 02/05/2007 SJ Full Version ;
; Revision Name ; ledwater ;
; Top-level Entity Name ; ledwater ;
; Family ; Cyclone ;
; Total logic elements ; 114 ;
; Total pins ; 14 ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 ;
; Total PLLs ; 1 ;
+------------------------+-----------------------------------------+
+---------------------------------------------------------------------------------------+
; Partition Merge Netlist Types Used ;
+----------------+------------------------+------------------------+--------------------+
; Partition Name ; Netlist Type Used ; Netlist Type Requested ; Partition Contents ;
+----------------+------------------------+------------------------+--------------------+
; Top ; Post-Synthesis Netlist ; Post-Synthesis Netlist ; ;
+----------------+------------------------+------------------------+--------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Partition Merge Partition Statistics ;
+----------------+----------------+-------------+--------------+------------------------+-------------------------+-------------------------+--------------------------+---------------------------+------------------------+--------------------+
; Partition Name ; Logic Elements ; Input Ports ; Output Ports ; Registered Input Ports ; Registered Output Ports ; Unconnected Input Ports ; Unconnected Output Ports ; Driven Ground Input Ports ; Driven VCC Input Ports ; Partition Contents ;
+----------------+----------------+-------------+--------------+------------------------+-------------------------+-------------------------+--------------------------+---------------------------+------------------------+--------------------+
; Top ; 115 ; 3 ; 11 ; 2 ; 0 ; N/A ; N/A ; N/A ; N/A ; ;
+----------------+----------------+-------------+--------------+------------------------+-------------------------+-------------------------+--------------------------+---------------------------+------------------------+--------------------+
+--------------------------------------------------------------------------------------+
; Partition Merge Resource Usage Summary ;
+---------------------------------------------+----------------------------------------+
; Resource ; Usage ;
+---------------------------------------------+----------------------------------------+
; Total logic elements ; 114 ;
; -- Combinational with no register ; 44 ;
; -- Register only ; 32 ;
; -- Combinational with a register ; 38 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 42 ;
; -- 3 input functions ; 33 ;
; -- 2 input functions ; 7 ;
; -- 1 input functions ; 0 ;
; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 77 ;
; -- arithmetic mode ; 37 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 0 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 70 ;
; Total logic cells in carry chains ; 38 ;
; I/O pins ; 14 ;
; Total PLLs ; 1 ;
; Maximum fan-out node ; pll20:u1|altpll:altpll_component|_clk0 ;
; Maximum fan-out ; 39 ;
; Total fan-out ; 395 ;
; Average fan-out ; 3.06 ;
+---------------------------------------------+----------------------------------------+
+--------------------------+
; Partition Merge Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Partition Merge
Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
Info: Processing started: Tue Aug 28 20:40:18 2007
Info: Command: quartus_cdb --read_settings_files=off --write_settings_files=off ledwater -c ledwater --merge=on
Info: Using synthesis netlist for partition "Top"
Info: Netlist merging resolved 1 partition(s) out of the 1 partition(s) found
Warning: Output port clk0 of PLL "pll20:u1|altpll:altpll_component|pll" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
Info: Quartus II Partition Merge was successful. 0 errors, 1 warning
Info: Allocated 95 megabytes of memory during processing
Info: Processing ended: Tue Aug 28 20:40:19 2007
Info: Elapsed time: 00:00:01
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