?? ledwater.tan.rpt
字號:
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1C3T144C8 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; pll20:u1|altpll:altpll_component|_clk0 ; ; PLL output ; 180.02 MHz ; 0.000 ns ; 0.000 ns ; clk ; 9 ; 1 ; -1.833 ns ; ;
; clk ; ; User Pin ; 20.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; sck ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+----------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'pll20:u1|altpll:altpll_component|_clk0' ;
+-----------------------------------------+-----------------------------------------------------+---------+---------+----------------------------------------+----------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------+---------+----------------------------------------+----------------------------------------+-----------------------------+---------------------------+-------------------------+
; 1.996 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; cnt[0] ; Ram0~19 ; pll20:u1|altpll:altpll_component|_clk0 ; pll20:u1|altpll:altpll_component|_clk0 ; 5.555 ns ; 5.294 ns ; 3.298 ns ;
; 1.996 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; cnt[0] ; Ram0~18 ; pll20:u1|altpll:altpll_component|_clk0 ; pll20:u1|altpll:altpll_component|_clk0 ; 5.555 ns ; 5.294 ns ; 3.298 ns ;
; 1.996 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; cnt[0] ; Ram0~17 ; pll20:u1|altpll:altpll_component|_clk0 ; pll20:u1|altpll:altpll_component|_clk0 ; 5.555 ns ; 5.294 ns ; 3.298 ns ;
; 1.996 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; cnt[0] ; Ram0~20 ; pll20:u1|altpll:altpll_component|_clk0 ; pll20:u1|altpll:altpll_component|_clk0 ; 5.555 ns ; 5.294 ns ; 3.298 ns ;
; 2.070 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; cnt[1] ; Ram0~19 ; pll20:u1|altpll:altpll_component|_clk0 ; pll20:u1|altpll:altpll_component|_clk0 ; 5.555 ns ; 5.294 ns ; 3.224 ns ;
; 2.070 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; cnt[1] ; Ram0~18 ; pll20:u1|altpll:altpll_component|_clk0 ; pll20:u1|altpll:altpll_component|_clk0 ; 5.555 ns ; 5.294 ns ; 3.224 ns ;
; 2.070 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; cnt[1] ; Ram0~17 ; pll20:u1|altpll:altpll_component|_clk0 ; pll20:u1|altpll:altpll_component|_clk0 ; 5.555 ns ; 5.294 ns ; 3.224 ns ;
; 2.070 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; cnt[1] ; Ram0~20 ; pll20:u1|altpll:altpll_component|_clk0 ; pll20:u1|altpll:altpll_component|_clk0 ; 5.555 ns ; 5.294 ns ; 3.224 ns ;
; 2.073 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; cnt[0] ; cnt[29] ; pll20:u1|altpll:altpll_component|_clk0 ; pll20:u1|altpll:altpll_component|_clk0 ; 5.555 ns ; 5.294 ns ; 3.221 ns ;
; 2.073 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; cnt[0] ; cnt[30] ; pll20:u1|altpll:altpll_component|_clk0 ; pll20:u1|altpll:altpll_component|_clk0 ; 5.555 ns ; 5.294 ns ; 3.221 ns ;
; 2.073 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; cnt[0] ; cnt[31] ; pll20:u1|altpll:altpll_component|_clk0 ; pll20:u1|altpll:altpll_component|_clk0 ; 5.555 ns ; 5.294 ns ; 3.221 ns ;
; 2.073 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; cnt[0] ; Ram0~15 ; pll20:u1|altpll:altpll_component|_clk0 ; pll20:u1|altpll:altpll_component|_clk0 ; 5.555 ns ; 5.294 ns ; 3.221 ns ;
; 2.073 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; cnt[0] ; Ram0~16 ; pll20:u1|altpll:altpll_component|_clk0 ; pll20:u1|altpll:altpll_component|_clk0 ; 5.555 ns ; 5.294 ns ; 3.221 ns ;
; 2.109 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; cnt[5] ; Ram0~19 ; pll20:u1|altpll:altpll_component|_clk0 ; pll20:u1|altpll:altpll_component|_clk0 ; 5.555 ns ; 5.294 ns ; 3.185 ns ;
; 2.109 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; cnt[5] ; Ram0~18 ; pll20:u1|altpll:altpll_component|_clk0 ; pll20:u1|altpll:altpll_component|_clk0 ; 5.555 ns ; 5.294 ns ; 3.185 ns ;
; 2.109 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; cnt[5] ; Ram0~17 ; pll20:u1|altpll:altpll_component|_clk0 ; pll20:u1|altpll:altpll_component|_clk0 ; 5.555 ns ; 5.294 ns ; 3.185 ns ;
; 2.109 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; cnt[5] ; Ram0~20 ; pll20:u1|altpll:altpll_component|_clk0 ; pll20:u1|altpll:altpll_component|_clk0 ; 5.555 ns ; 5.294 ns ; 3.185 ns ;
; 2.147 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; cnt[1] ; cnt[29] ; pll20:u1|altpll:altpll_component|_clk0 ; pll20:u1|altpll:altpll_component|_clk0 ; 5.555 ns ; 5.294 ns ; 3.147 ns ;
; 2.147 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; cnt[1] ; cnt[30] ; pll20:u1|altpll:altpll_component|_clk0 ; pll20:u1|altpll:altpll_component|_clk0 ; 5.555 ns ; 5.294 ns ; 3.147 ns ;
?? 快捷鍵說明
復制代碼
Ctrl + C
搜索代碼
Ctrl + F
全屏模式
F11
切換主題
Ctrl + Shift + D
顯示快捷鍵
?
增大字號
Ctrl + =
減小字號
Ctrl + -