{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Partition Merge Quartus II " "Info: Running Quartus II Partition Merge" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Aug 28 20:40:18 2007 " "Info: Processing started: Tue Aug 28 20:40:18 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_cdb --read_settings_files=off --write_settings_files=off ledwater -c ledwater --merge=on " "Info: Command: quartus_cdb --read_settings_files=off --write_settings_files=off ledwater -c ledwater --merge=on" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IAMERGE_PARTITION_SOURCE_SOURCE" "Top " "Info: Using synthesis netlist for partition \"Top\"" {  } {  } 0 0 "Using synthesis netlist for partition \"%1!s!\"" 0 0}
{ "Info" "IAMERGE_ATOM_BLACKBOX_RESOLVED" "1 1 " "Info: Netlist merging resolved 1 partition(s) out of the 1 partition(s) found" {  } {  } 0 0 "Netlist merging resolved %1!d! partition(s) out of the %2!d! partition(s) found" 0 0}
{ "Warning" "WCUT_CUT_YGR_PLL_BAD_FANOUT_CLK3" "clk0 pll20:u1\|altpll:altpll_component\|pll " "Warning: Output port clk0 of PLL \"pll20:u1\|altpll:altpll_component\|pll\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" {  } { { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } } { "pll20.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/pll20.vhd" 136 0 0 } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 137 0 0 } }  } 0 0 "Output port %1!s! of PLL \"%2!s!\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Partition Merge 0 s 1  Quartus II " "Info: Quartus II Partition Merge was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "95 " "Info: Allocated 95 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Aug 28 20:40:19 2007 " "Info: Processing ended: Tue Aug 28 20:40:19 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}