{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "sck " "Info: Assuming node \"sck\" is an undefined clock" {  } { { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 10 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "sck" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "pll20:u1\|altpll:altpll_component\|_clk0 register cnt\[0\] register Ram0~19 1.996 ns " "Info: Slack time is 1.996 ns for clock \"pll20:u1\|altpll:altpll_component\|_clk0\" between source register \"cnt\[0\]\" and destination register \"Ram0~19\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT_RESTRICTED" "275.03 MHz " "Info: Fmax is restricted to 275.03 MHz due to tcl and tch limits" {  } {  } 0 0 "Fmax is restricted to %1!s! due to tcl and tch limits" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "5.294 ns + Largest register register " "Info: + Largest register to register requirement is 5.294 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "5.555 ns + " "Info: + Setup relationship between source and destination is 5.555 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 3.722 ns " "Info: + Latch edge is 3.722 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll20:u1\|altpll:altpll_component\|_clk0 5.555 ns -1.833 ns  50 " "Info: Clock period of Destination clock \"pll20:u1\|altpll:altpll_component\|_clk0\" is 5.555 ns with  offset of -1.833 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.833 ns " "Info: - Launch edge is -1.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll20:u1\|altpll:altpll_component\|_clk0 5.555 ns -1.833 ns  50 " "Info: Clock period of Source clock \"pll20:u1\|altpll:altpll_component\|_clk0\" is 5.555 ns with  offset of -1.833 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll20:u1\|altpll:altpll_component\|_clk0 destination 2.318 ns + Shortest register " "Info: + Shortest clock path from clock \"pll20:u1\|altpll:altpll_component\|_clk0\" to destination register is 2.318 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll20:u1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 39 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 39; CLK Node = 'pll20:u1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll20:u1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.607 ns) + CELL(0.711 ns) 2.318 ns Ram0~19 2 REG LC_X16_Y8_N7 24 " "Info: 2: + IC(1.607 ns) + CELL(0.711 ns) = 2.318 ns; Loc. = LC_X16_Y8_N7; Fanout = 24; REG Node = 'Ram0~19'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 Ram0~19 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 30.67 % ) " "Info: Total cell delay = 0.711 ns ( 30.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.607 ns ( 69.33 % ) " "Info: Total interconnect delay = 1.607 ns ( 69.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 Ram0~19 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 Ram0~19 } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll20:u1\|altpll:altpll_component\|_clk0 source 2.318 ns - Longest register " "Info: - Longest clock path from clock \"pll20:u1\|altpll:altpll_component\|_clk0\" to source register is 2.318 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll20:u1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 39 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 39; CLK Node = 'pll20:u1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { pll20:u1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/70/quartus/libraries/megafunctions/altpll.tdf" 871 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.607 ns) + CELL(0.711 ns) 2.318 ns cnt\[0\] 2 REG LC_X16_Y11_N1 3 " "Info: 2: + IC(1.607 ns) + CELL(0.711 ns) = 2.318 ns; Loc. = LC_X16_Y11_N1; Fanout = 3; REG Node = 'cnt\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[0] } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 30.67 % ) " "Info: Total cell delay = 0.711 ns ( 30.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.607 ns ( 69.33 % ) " "Info: Total interconnect delay = 1.607 ns ( 69.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[0] } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 Ram0~19 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 Ram0~19 } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[0] } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 39 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 Ram0~19 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 Ram0~19 } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[0] } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.298 ns - Longest register register " "Info: - Longest register to register delay is 3.298 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[0\] 1 REG LC_X16_Y11_N1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X16_Y11_N1; Fanout = 3; REG Node = 'cnt\[0\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { cnt[0] } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.529 ns) + CELL(0.564 ns) 1.093 ns cnt\[0\]~165 2 COMB LC_X16_Y11_N1 2 " "Info: 2: + IC(0.529 ns) + CELL(0.564 ns) = 1.093 ns; Loc. = LC_X16_Y11_N1; Fanout = 2; COMB Node = 'cnt\[0\]~165'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.093 ns" { cnt[0] cnt[0]~165 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.171 ns cnt\[1\]~164 3 COMB LC_X16_Y11_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.171 ns; Loc. = LC_X16_Y11_N2; Fanout = 2; COMB Node = 'cnt\[1\]~164'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { cnt[0]~165 cnt[1]~164 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 1.249 ns cnt\[2\]~163 4 COMB LC_X16_Y11_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.249 ns; Loc. = LC_X16_Y11_N3; Fanout = 2; COMB Node = 'cnt\[2\]~163'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.078 ns" { cnt[1]~164 cnt[2]~163 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 1.427 ns cnt\[3\]~162 5 COMB LC_X16_Y11_N4 6 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.427 ns; Loc. = LC_X16_Y11_N4; Fanout = 6; COMB Node = 'cnt\[3\]~162'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.178 ns" { cnt[2]~163 cnt[3]~162 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 1.635 ns cnt\[8\]~157 6 COMB LC_X16_Y11_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.208 ns) = 1.635 ns; Loc. = LC_X16_Y11_N9; Fanout = 6; COMB Node = 'cnt\[8\]~157'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.208 ns" { cnt[3]~162 cnt[8]~157 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 1.771 ns cnt\[13\]~152 7 COMB LC_X16_Y10_N4 6 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 1.771 ns; Loc. = LC_X16_Y10_N4; Fanout = 6; COMB Node = 'cnt\[13\]~152'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { cnt[8]~157 cnt[13]~152 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 1.979 ns cnt\[18\]~147 8 COMB LC_X16_Y10_N9 6 " "Info: 8: + IC(0.000 ns) + CELL(0.208 ns) = 1.979 ns; Loc. = LC_X16_Y10_N9; Fanout = 6; COMB Node = 'cnt\[18\]~147'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.208 ns" { cnt[13]~152 cnt[18]~147 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.115 ns cnt\[23\]~142 9 COMB LC_X16_Y9_N4 6 " "Info: 9: + IC(0.000 ns) + CELL(0.136 ns) = 2.115 ns; Loc. = LC_X16_Y9_N4; Fanout = 6; COMB Node = 'cnt\[23\]~142'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { cnt[18]~147 cnt[23]~142 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 2.323 ns cnt\[28\]~137 10 COMB LC_X16_Y9_N9 6 " "Info: 10: + IC(0.000 ns) + CELL(0.208 ns) = 2.323 ns; Loc. = LC_X16_Y9_N9; Fanout = 6; COMB Node = 'cnt\[28\]~137'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.208 ns" { cnt[23]~142 cnt[28]~137 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 115 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 2.459 ns Ram0~1556 11 COMB LC_X16_Y8_N4 4 " "Info: 11: + IC(0.000 ns) + CELL(0.136 ns) = 2.459 ns; Loc. = LC_X16_Y8_N4; Fanout = 4; COMB Node = 'Ram0~1556'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.136 ns" { cnt[28]~137 Ram0~1556 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 3.298 ns Ram0~19 12 REG LC_X16_Y8_N7 24 " "Info: 12: + IC(0.000 ns) + CELL(0.839 ns) = 3.298 ns; Loc. = LC_X16_Y8_N7; Fanout = 24; REG Node = 'Ram0~19'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.839 ns" { Ram0~1556 Ram0~19 } "NODE_NAME" } } { "ledwater.vhd" "" { Text "E:/DDFS_PLL_10DA_with51/ledwater.vhd" 39 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.769 ns ( 83.96 % ) " "Info: Total cell delay = 2.769 ns ( 83.96 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.529 ns ( 16.04 % ) " "Info: Total interconnect delay = 0.529 ns ( 16.04 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.298 ns" { cnt[0] cnt[0]~165 cnt[1]~164 cnt[2]~163 cnt[3]~162 cnt[8]~157 cnt[13]~152 cnt[18]~147 cnt[23]~142 cnt[28]~137 Ram0~1556 Ram0~19 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.298 ns" { cnt[0] cnt[0]~165 cnt[1]~164 cnt[2]~163 cnt[3]~162 cnt[8]~157 cnt[13]~152 cnt[18]~147 cnt[23]~142 cnt[28]~137 Ram0~1556 Ram0~19 } { 0.000ns 0.529ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.208ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.839ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 Ram0~19 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 Ram0~19 } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.318 ns" { pll20:u1|altpll:altpll_component|_clk0 cnt[0] } { 0.000ns 1.607ns } { 0.000ns 0.711ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "3.298 ns" { cnt[0] cnt[0]~165 cnt[1]~164 cnt[2]~163 cnt[3]~162 cnt[8]~157 cnt[13]~152 cnt[18]~147 cnt[23]~142 cnt[28]~137 Ram0~1556 Ram0~19 } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "3.298 ns" { cnt[0] cnt[0]~165 cnt[1]~164 cnt[2]~163 cnt[3]~162 cnt[8]~157 cnt[13]~152 cnt[18]~147 cnt[23]~142 cnt[28]~137 Ram0~1556 Ram0~19 } { 0.000ns 0.529ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 0.564ns 0.078ns 0.078ns 0.178ns 0.208ns 0.136ns 0.208ns 0.136ns 0.208ns 0.136ns 0.839ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}